SCPS270B August   2020  – November 2023 TCA4307

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Hot bus insertion
      2. 7.3.2 Pre-charge voltage
      3. 7.3.3 Rise time accelerators
      4. 7.3.4 Bus ready output indicator
      5. 7.3.5 Powered-off high impedance for I2C and I/O pins
      6. 7.3.6 Supports clock stretching and arbitration
      7. 7.3.7 Stuck bus recovery
    4. 7.4 Device Functional Modes
      1. 7.4.1 Start-up and precharge
      2. 7.4.2 Bus idle
      3. 7.4.3 Bus active
      4. 7.4.4 Bus stuck
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Series connections
        2. 8.2.1.2 Multiple connections to a common node
        3. 8.2.1.3 Propagation delays
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Typical Application on a Backplane
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Best Practices
      2. 8.3.2 Power-on Reset Requirements
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.1 Series connections

It is possible to have multiple buffers in series, but care must be taken when designing a system.

GUID-3F90F715-EEC5-4277-8A45-308BAB7ABCC8-low.gifFigure 8-2 Series Buffer Connections

Each buffer adds approximately 60 mV of offset. Maximum offset (VOFFSET) should be considered. The low level at the signal origination end is dependent upon bus load. The I2C-bus specification requires that a 3 mA current produces no larger than a 0.4 V VOL. As an example, if the VOL at the controller is 0.1 V, and there are 4 buffers in series (each adding about 60 mV), then the VOL at the farthest buffer is approximately 0.34 V. This device has a rise time accelerator (RTA) that activates at 0.6 V. With great care, a system with 4 buffers may work, but as the VOL moves up, it may be possible to trigger the RTA, creating a false edge on the clock.

It is recommended to limit the number of buffers in series to two, and to keep the load light to minimize the offset.

Another special consideration of series connections is the effect on round-trip-delay. This is the sum of propagation delays through the buffers and any effects on rise time. It is possible that fast mode speeds (400 kHz) are not possible due to delays and bus loading.