SCPS234A September   2016  – February 2023 TCA6408A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Translation
      2. 8.3.2 I/O Port
      3. 8.3.3 Interrupt Output ( INT)
      4. 8.3.4 Reset Input ( RESET)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset (POR)
      2. 8.4.2 Powered-Up
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Bus Transactions
        1. 8.5.2.1 Writes
        2. 8.5.2.2 Reads
    6. 8.6 Register Map
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
      3. 8.6.3 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Calculating Junction Temperature and Power Dissipation
        2. 9.2.1.2 Minimizing ICC When I/O is Used to Control LEDs
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-On Reset Requirements
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Trademarks
    3. 10.3 Electrostatic Discharge Caution
    4. 10.4 Glossary
  11. 11Support Resources
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.3.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCA6408A-Q1 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

Ramping up the device VCCP before VCCI is recommended to prevent SDA from potentially being stuck LOW.

The two types of power-on reset are shown in Figure 9-6 and Figure 9-7.

GUID-7A046B05-122E-4D47-8FDB-D59D879A6D84-low.gifFigure 9-6 VCCP is Lowered Below 0.2 V and then Ramped Up to VCCP
GUID-B0315882-6336-4DCA-A0BA-A41887818A7B-low.gifFigure 9-7 VCCP is Lowered Below the POR Threshold, then Ramped Back Up to VCCP

Table 9-1 specifies the performance of the power-on reset feature for TCA6408A-Q1 for both types of power-on reset.

Table 9-1 Recommended Supply Sequencing and Ramp Rates at TA = 25°C(1)
PARAMETERMINTYPMAXUNIT
tFTFall rateSee Figure 9-60.12000ms
tRTRise rateSee Figure 9-60.12000ms
tRR_GNDTime to re-ramp (when VCCP drops to GND)See Figure 9-61μs
tRR_POR50Time to re-ramp (when VCCP drops to VPOR_MIN – 50 mV)See Figure 9-71μs
VCCP_GHLevel that VCCP can glitch down from VCCP, but not cause a functional disruption when tVCCP_GW = 1 μsSee Figure 9-81.2V
VCCP_MVThe minimum voltage that VCC can glitch down to without causing a reset (VCC_GH must not be violated)See Figure 9-81.5V
tVCCP_GWGlitch width that does not cause a functional disruption when tVCCP_GH = 0.5 × VCCxSee Figure 9-810μs
VPORFVoltage trip point of POR on falling VCCP0.61V
VPORRVoltage trip point of POR on rising VCCP1.21.5V
(1) Not tested. Specified by design.

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (tVCCP_GW) and height (VCCP_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 9-8 and Table 9-1 provide more information on how to measure these specifications.

GUID-6DD945F0-85CC-4B80-A21D-4E9ADFBF7BB3-low.gifFigure 9-8 Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPORR / VPORF is the voltage level at which the reset condition is released/asserted and all the registers and the I2C/SMBus state machine are initialized to the default states (upon a release of a reset condition). The voltage that the device has a reset condition asserted or released differs based on whether VCCP is being lowered to or from 0. Figure 9-9 and Table 9-1 provide more details on this specification.

GUID-DC2BDCE0-8156-466F-B083-40ACF0DCA872-low.gifFigure 9-9 Power On Reset