SCPS193C July   2010  – April 2014 TCA6424A

PRODUCTION DATA.  

  1. Features
  2. Description
  3. Revision History
  4. Description (continued)
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 I2C Interface Timing Requirements
    6. 6.6 Reset Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Voltage Translation
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 I2C Interface
      3. 8.3.3 Device Address
    4. 8.4 Programming
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Reset Input (RESET)
      3. 8.4.3 Interrupt Output (INT)
      4. 8.4.4 Bus Transactions
        1. 8.4.4.1 Writes
        2. 8.4.4.2 Reads
    5. 8.5 Register Maps
      1. 8.5.1 Control Register and Command Byte
      2. 8.5.2 Register Descriptions
  9. Applications and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Minimizing ICC When I/Os Control LEDs
  10. 10Power Supply Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Detailed Description

8.1 Overview

8.1.1 Voltage Translation

Table 1 shows how to set up VCC levels for the necessary voltage translation between the I2C bus and the TCA6424A.

Table 1. Voltage Translation

VCCI (SDA AND SCL OF I2C MASTER)
(V)
VCCP (P PORT)
(V)
1.8 1.8
1.8 2.5
1.8 3.3
1.8 5
2.5 1.8
2.5 2.5
2.5 3.3
2.5 5
3.3 1.8
3.3 2.5
3.3 3.3
3.3 5
5 1.8
5 2.5
5 3.3
5 5

8.2 Functional Block Diagram

ld_cps175.gif
A. All I/Os are set to inputs at reset.
B. Pin numbers shown are for the RGJ package.
Figure 18. Positive Logic
simpl_ios_cps175.gif
A. On power up or reset, all registers return to default values.
Figure 19. Simplified Schematic of P00 to P27

8.3 Feature Description

8.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage applied to this I/O pin should not exceed the recommended levels for proper operation.

8.3.2 I2C Interface

The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output, while the SCL input is high (see Figure 20). After the Start condition, the device address byte is sent, most significant bit (MSB) first, including the data direction bit (R/W).

After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must not be changed between the Start and the Stop conditions.

On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 21).

A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 20).

Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 22). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation.

A master receiver signals an end of data to the slave transmitter by not generating an acknowledge (NACK) after the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high. In this event, the transmitter must release the data line to enable the master to generate a Stop condition.

def_start_cps175.gifFigure 20. Definition of Start and Stop Conditions
bit_trans_cps175.gifFigure 21. Bit Transfer
ack_i2c_cps175.gifFigure 22. Acknowledgment on the I2C Bus

Table 2. Interface Definition

BYTE BIT
7 (MSB) 6 5 4 3 2 1 0 (LSB)
I2C slave address L H L L L H ADDR R/W
I/O data bus P07 P06 P05 P04 P03 P02 P01 P00
P17 P16 P15 P14 P13 P12 P11 P10
P27 P26 P25 P24 P23 P22 P21 P20

8.3.3 Device Address

The address of the TCA6424A is shown in Figure 23.

address_cps175.gifFigure 23. TCA6424A Address

Table 3. Address Reference

ADDR I2C BUS SLAVE ADDRESS
L 34 (decimal), 22 (hexadecimal)
H 35 (decimal), 23 (hexadecimal)

The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read operation, while a low (0) selects a write operation.

8.4 Programming

8.4.1 Power-On Reset

When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6424A in a reset condition until VCCP has reached VPOR. At that time, the reset condition is released, and the TCA6424A registers and I2C/SMBus state machine initializes to their default states. After that, VCCP must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle.

8.4.2 Reset Input (RESET)

The RESET input can be asserted to initialize the system while keeping the VCCP at its operating level. A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TCA6424A registers and I2C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1), the I/O levels at the P port can be changed externally or through the master. This input requires a pullup resistor to VCCI, if no active connection is used.

8.4.3 Interrupt Output (INT)

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the state of the pin does not match the contents of the Input Port register.

The INT output has an open-drain structure and requires pullup resistor to VCCP or VCCI depending on the application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA6424A then the INT pin has to be connected to VCCI. If not, the INT pin can be connected to VCCP.

8.4.4 Bus Transactions

Data is exchanged between the master and TCA6424A through write and read commands.

8.4.4.1 Writes

Data is transmitted to the TCA6424A by sending the device address and setting the least-significant bit (LSB) to a logic 0 (see Figure 23 for device address). The command byte is sent after the address and determines which register receives the data that follows the command byte. There is no limitation on the number of data bytes sent in one write transmission.

The twelve registers within the TCA6424A are grouped into four different sets. The four sets of registers are input ports, output ports, polarity inversion ports and configuration ports. After sending data to one register, the next data byte is sent to the next register in the group of 3 registers (see Figure 24 and Figure 25). For example, if the first byte is send to Output Port 2 (register 6), the next byte is stored in Output Port 0 (register 4).

There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers.

wr_out_reg_cps175.gifFigure 24. Write to Output Port Register

wr_cfg_reg_cps175.gifFigure 25. Write to Configuration or Polarity Inversion Registers

8.4.4.2 Reads

The bus master first must send the TCA6424A address with the LSB set to a logic 0 (see Figure 23 for device address). The command byte is sent after the address and determines which register is accessed.

After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the TCA6424A (see Figure 26 and Figure 27).

After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0.

Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data.

rd_reg_cps175.gifFigure 26. Read From Register

rd_input_cps175.gif
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from P port (see Figure 26).
C. Auto-increment mode is enabled.
Figure 27. Read Input Port Register

8.5 Register Maps

8.5.1 Control Register and Command Byte

Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is stored in the control register in the TCA6424A. Four bits of this data byte state the operation (read or write) and the internal registers (input, output, polarity inversion, or configuration) that will be affected. The control register can be written or read through the I2C bus. The command byte is sent only during a write transmission.

The control register includes an Auto-Increment (AI) bit which is the most significant bit (bit 7) of the command byte. At power-up, the control register defaults to 00 (hex), with the AI bit set to logic 1, and the lowest 7 bits set to logic 0.

If AI is 1, the 2 least significant bits are automatically incremented after a read or write. This allows the user to program and/or read the 3 register banks sequentially. If more than 3 bytes of data are written when AI is 1, previous data in the selected registers will be overwritten. Reserved registers are skipped and not accessed (refer to Table 5).

If AI is 0, the 2 least significant bits are not incremented after data is read or written. During a read operation, the same register bank is read each time. During a write operation, data is written to the same register bank each time.

Reserved command codes and command byte outside the range stated in the Command Byte table must not be accessed for proper device functionality.

cntrl_reg_cps175.gifFigure 28. Control Register Bits

Table 4. Command Byte

CONTROL REGISTER BITS AUTO-INCREMENT STATE COMMAND BYTE
(HEX)
REGISTER PROTOCOL POWER-UP
DEFAULT
AI B6 B5 B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 Disable 00 Input Port 0 Read byte xxxx xxxx(1)
1 0 0 0 0 0 0 0 Enable 80
0 0 0 0 0 0 0 1 Disable 01 Input Port 1 Read byte xxxx xxxx(1)
1 0 0 0 0 0 0 1 Enable 81
0 0 0 0 0 0 1 0 Disable 02 Input Port 2 Read byte xxxx xxxx(1)
1 0 0 0 0 0 1 0 Enable 82
0 0 0 0 0 0 1 1 Disable 03 Reserved Reserved Reserved
1 0 0 0 0 0 1 1 Enable 83
0 0 0 0 0 1 0 0 Disable 04 Output Port 0 Read/write byte 1111 1111
1 0 0 0 0 1 0 0 Enable 84
0 0 0 0 0 1 0 1 Disable 05 Output Port 1 Read/write byte 1111 1111
1 0 0 0 0 1 0 1 Enable 85
0 0 0 0 0 1 1 0 Disable 06 Output Port 2 Read/write byte 1111 1111
1 0 0 0 0 1 1 0 Enable 86
0 0 0 0 0 1 1 1 Disable 07 Reserved Reserved Reserved
1 0 0 0 0 1 1 1 Enable 87
0 0 0 0 1 0 0 0 Disable 08 Polarity Inversion Port 0 Read/write byte 0000 0000
1 0 0 0 1 0 0 0 Enable 88
0 0 0 0 1 0 0 1 Disable 09 Polarity Inversion Port 1 Read/write byte 0000 0000
1 0 0 0 1 0 0 1 Enable 89
0 0 0 0 1 0 1 0 Disable 0A Polarity Inversion Port 2 Read/write byte 0000 0000
1 0 0 0 1 0 1 0 Enable 8A
0 0 0 0 1 0 1 1 Disable 0B Reserved Reserved Reserved
1 0 0 0 1 0 1 1 Enable 8B
0 0 0 0 1 1 0 0 Disable 0C Configuration Port 0 Read/write byte 1111 1111
1 0 0 0 1 1 0 0 Enable 8C
0 0 0 0 1 1 0 1 Disable 0D Configuration Port 1 Read/write byte 1111 1111
1 0 0 0 1 1 0 1 Enable 8D
0 0 0 0 1 1 1 0 Disable 0E Configuration Port 2 Read/write byte 1111 1111
1 0 0 0 1 1 1 0 Enable 8E
0 0 0 0 1 1 1 1 Disable 0F Reserved Reserved Reserved
1 0 0 0 1 1 1 1 Enable 8F
(1) Undefined

8.5.2 Register Descriptions

The Input Port registers (registers 0, 1 and 2) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. They act only on read operation. Writes to these registers have no effect. The default value (X) is determined by the externally applied logic level. Before a read operation, a write transmission is sent with the command byte to indicate to the I2C device that the Input Port register will be accessed next.

Table 5. Registers 0, 1 and 2 (Input Port Registers)

BIT I-07 I-06 I-05 I-04 I-03 I-02 I-01 I-00
DEFAULT X X X X X X X X
BIT I-17 I-16 I-15 I-14 I-13 I-12 I-11 I-10
DEFAULT X X X X X X X X
BIT I-27 I-26 I-25 I-24 I-23 I-22 I-21 I-20
DEFAULT X X X X X X X X

The Output Port registers (registers 4, 5 and 6) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in these registers have no effect on pins defined as inputs. In turn, reads from these registers reflect the value that is in the flip-flop controlling the output selection, NOT the actual pin value.

Table 6. Registers 4, 5 and 6 (Output Port Registers)

BIT O-07 O-06 O-05 O-04 O-03 O-02 O-01 O-00
DEFAULT 1 1 1 1 1 1 1 1
BIT O-17 O-16 O-15 O-14 O-13 O-12 O-11 O-10
DEFAULT 1 1 1 1 1 1 1 1
BIT O-27 O-26 O-25 O-24 O-23 O-22 O-21 O-20
DEFAULT 1 1 1 1 1 1 1 1

The Polarity Inversion registers (registers 8, 9 and 10) allow polarity inversion of pins defined as inputs by the Configuration register. If a bit in these registers is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in these registers is cleared (written with a 0), the corresponding port pin's original polarity is retained.

Table 7. Registers 8, 9 and 10 (Polarity Inversion Registers)

BIT P-07 P-06 P-05 P-04 P-03 P-02 P-01 P-00
DEFAULT 0 0 0 0 0 0 0 0
BIT P-17 P-16 P-15 P-14 P-13 P-12 P-11 P-10
DEFAULT 0 0 0 0 0 0 0 0
BIT P-27 P-26 P-25 P-24 P-23 P-22 P-21 P-20
DEFAULT 0 0 0 0 0 0 0 0

The Configuration registers (registers 12, 13 and 14) configure the direction of the I/O pins. If a bit in these registers is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in these registers is cleared to 0, the corresponding port pin is enabled as an output.

Table 8. Registers 12, 13 and 14 (Configuration Registers)

BIT C-07 C-06 C-05 C-04 C-03 C-02 C-01 C-00
DEFAULT 1 1 1 1 1 1 1 1
BIT C-17 C-16 C-15 C-14 C-13 C-12 C-11 C-10
DEFAULT 1 1 1 1 1 1 1 1
BIT C-27 C-26 C-25 C-24 C-23 C-22 C-21 C-20
DEFAULT 1 1 1 1 1 1 1 1