SCPS193C July   2010  – April 2014 TCA6424A


  1. Features
  2. Description
  3. Revision History
  4. Description (continued)
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 I2C Interface Timing Requirements
    6. 6.6 Reset Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Voltage Translation
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 I2C Interface
      3. 8.3.3 Device Address
    4. 8.4 Programming
      1. 8.4.1 Power-On Reset
      2. 8.4.2 Reset Input (RESET)
      3. 8.4.3 Interrupt Output (INT)
      4. 8.4.4 Bus Transactions
        1. Writes
        2. Reads
    5. 8.5 Register Maps
      1. 8.5.1 Control Register and Command Byte
      2. 8.5.2 Register Descriptions
  9. Applications and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Minimizing ICC When I/Os Control LEDs
  10. 10Power Supply Recommendation
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendation

In the event of a glitch or data corruption, TCA6424A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 32 and Figure 33.

pwron01_cps193.gifFigure 32. VCC is Lowered Below 0.2 V or 0 V and Then Ramped Up to VCC
pwron02_cps193.gifFigure 33. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC

Table 9 specifies the performance of the power-on reset feature for TCA6424A for both types of power-on reset.

Table 9. Recommended Supply Sequencing and Rates(1)

tVCC_FT Fall rate See Figure 32 1 100 ms
tVCC_RT Rise rate See Figure 32 0.01 100 ms
tVCC_TRR_GND Time to re-ramp (when VCC drops to GND) See Figure 32 40 μs
tVCC_TRR_POR50 Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) See Figure 33 40 μs
VCC_GH Level that VCCP can glitch down to, but not cause a functional disruption when VCCX_GW = 1 μs See Figure 34 1.2 V
tVCC_GW Glitch width that will not cause a functional disruption when VCCX_GH = 0.5 × VCCx See Figure 34 10 μs
VPORF Voltage trip point of POR on falling VCC 0.767 1.144 V
VPORR Voltage trip point of POR on fising VCC 1.033 1.428 V
(1) TA = –40°C to 85°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 34 and Table 9 provide more information on how to measure these specifications.

pwron03_cps193.gifFigure 34. Glitch Width and Glitch Height

VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 35 and Table 9 provide more details on this specification.

pwron04_cps193.gifFigure 35. VPOR