SCPS237 June 2018 TCA9517-Q1
A typical application is shown in Figure 7. In this example, the system master is running on a 3.3 V I2C bus, and the slave is connected to a 1.2 V I2C bus. Both buses run at 400 kHz. Master devices can be placed on either bus.
The TCA9517-Q1 is 5-V tolerant, so it does not require any additional circuitry to translate between 0.9 V to 5.25 V bus voltages and 2.7 V to 5.25 V bus voltages.
When the A side of the TCA9517-Q1 is pulled low by a driver on the I2C bus, a comparator detects the falling edge when it goes below 0.3 × VCCA and causes the internal driver on the B-side to turn on, causing the B-side to pull down to about 0.5 V. When the B-side of the TCA9517-Q1 falls, first a CMOS hysteresis-type input detects the falling edge and causes the internal driver on the A side to turn on and pull the A-side pin down to ground. In order to illustrate what would be seen in a typical application, refer to Figure 9 and Figure 10. If the bus master in Figure 7 were to write to the slave through the TCA9517-Q1, waveforms shown in Figure 9 would be observed on the A bus. This looks like a normal I2C transmission, except that the high level may be as low as 0.9 V, and the turn on and turn off of the acknowledge signals are slightly delayed.
On the B-side bus of the TCA9517-Q1, the clock and data lines would have a positive offset from ground equal to the VOL of the TCA9517-Q1. After the eighth clock pulse, the data line is pulled to the VOL of the slave device, which is very close to ground in this example. At the end of the acknowledge, the level rises only to the low level set by the driver in the TCA9517-Q1 for a short delay, while the A-bus side rises above 0.3 × VCCA and then continues high.