SLLSET0C October   2016  – May 2017 TCAN1051-Q1 , TCAN1051G-Q1 , TCAN1051GV-Q1 , TCAN1051H-Q1 , TCAN1051HG-Q1 , TCAN1051HGV-Q1 , TCAN1051HV-Q1 , TCAN1051V-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configurations and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Power Rating
    6. 7.6 Electrical Characteristics
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TXD Dominant Timeout (DTO)
      2. 9.3.2 Thermal Shutdown (TSD)
      3. 9.3.3 Undervoltage Lockout
      4. 9.3.4 Unpowered Device
      5. 9.3.5 Floating Terminals
      6. 9.3.6 CAN Bus Short Circuit Current Limiting
      7. 9.3.7 Digital Inputs and Outputs
        1. 9.3.7.1 5-V VCC Only Devices (Devices without the "V" Suffix):
        2. 9.3.7.2 5 V VCC with VIO I/O Level Shifting (Devices with the "V" Suffix):
    4. 9.4 Device Functional Modes
      1. 9.4.1 CAN Bus States
      2. 9.4.2 Normal Mode
      3. 9.4.3 Silent Mode
      4. 9.4.4 Driver and Receiver Function Tables
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Bus Loading, Length and Number of Nodes
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 CAN Termination
      3. 10.2.3 Application Curves
  11. 11Power Supply Requirements
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DRB|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1) (2)

MIN MAX UNIT
VCC 5-V Bus Supply Voltage Range All Devices –0.3 7 V
VIO I/O Level-Shifting Voltage Range Devices with the "V" Suffix –0.3 7 V
VBUS CAN Bus I/O voltage range (CANH, CANL) Devices without the "H" Suffix –58 58 V
V(Diff) Max differential voltage between
CANH and CANL		 Devices without the “H” suffix –58 58 V
VBUS CAN Bus I/O voltage range (CANH, CANL) Devices with the "H" Suffix -70 70 V
V(Diff) Max differential voltage between
CANH and CANL		 Devices with the “H” suffix –70 70 V
V(Logic_Input) Logic input terminal voltage range (TXD, S) All Devices –0.3 +7 and VI ≤ VIO + 0.3 V
V(Logic_Output) Logic output terminal voltage range (RXD) –0.3 +7 and VI ≤ VIO + 0.3 V
IO(RXD) RXD (Receiver) output current –8 8 mA
TJ Virtual junction temperature range (see Thermal Information) –55 150 °C
TSTG Storage temperature range (see Thermal Information) –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated condition for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.

7.2 ESD Ratings

TEST CONDITIONS VALUE UNIT
D (SOIC) Package
Human Body Model (HBM) ESD stress voltage All terminals(1) ±6000 V
CAN bus terminals (CANH, CANL) to GND(2) ±16000
Charged Device Model (CDM) ESD stress voltage All terminals(3) ±1500 V
Machine Model All terminals(4) ±200 V
System Level Electro-Static Discharge (ESD) CAN bus terminals (CANH, CANL) to GND SAE J2962-2 per ISO 10605: Powered Air Discharge ±15000 V
SAE J2962-2 per ISO 10605: Powered Contact Discharge ±8000
System Level Electro-Static Discharge (ESD) CAN bus terminals (CANH, CANL) to GND IEC 61000-4-2: Unpowered Contact Discharge ±15000 V
IEC 61000-4-2: Powered Contact Discharge ±8000
System Level Electrical fast transient (EFT) CAN bus terminals (CANH, CANL) to GND IEC 61000-4-4: Criteria A ±4000 V
ISO7637 Transients according to GIFT - ICT CAN EMC test spec(5) CAN bus terminals (CANH, CANL) to GND Pulse 1 –100 V
Pulse 2 +75
Pulse 3a –150
Pulse 3b +100
ISO7637-3 Transients CAN bus terminals (CANH, CANL) to GND Direct Coupling Capacitor "Slow Transient Pulse" with100 nF coupling capacitor - Powered ±85 V
DRB (VSON) Package
Human Body Model (HBM) ESD stress voltage All terminals(1) ±6000 V
CAN bus terminals (CANH, CANL) to GND(2) ±16000
Charged Device Model (CDM) ESD stress voltage All terminals(3) ±1500 V
Machine Model All terminals(4) ±200 V
System Level Electro-Static Discharge (ESD) CAN bus terminals (CANH, CANL) to GND SAE J2962-2 per ISO 10605: Powered Air Discharge ±15000 V
SAE J2962-2 per ISO 10605: Powered Contact Discharge ±8000
System Level Electro-Static Discharge (ESD) CAN bus terminals (CANH, CANL) to GND IEC 61000-4-2: Unpowered Contact Discharge ±14000 V
IEC 61000-4-2: Powered Contact Discharge ±8000
System Level Electrical fast transient (EFT) CAN bus terminals (CANH, CANL) to GND IEC 61000-4 Criteria A ±4000 V
ISO7637 Transients according to GIFT - ICT CAN EMC test spec(5) CAN bus terminals (CANH, CANL) to GND Pulse 1 –100 V
Pulse 2 +75
Pulse 3a –150
Pulse 3b +100
ISO7637-3 Transients CAN bus terminals (CANH, CANL) to GND Direct Coupling Capacitor "Slow Transient Pulse" with100 nF coupling capacitor - Powered ±85 V
(1) Tested in accordance to JEDEC Standard 22, Test Method A114.
(2) Test method based upon JEDEC Standard 22 Test Method A114, CAN bus is stressed with respect to GND.
(3) Tested in accordance to JEDEC Standard 22, Test Method C101.
(4) Tested in accordance to JEDEC Standard 22, Test Method A115.
(5) ISO7637 is a system level transient test. Results given here are specific to the GIFT-ICT CAN EMC Test specification conditions. Different system level configurations may lead to different results.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VCC 5-V Bus Supply Voltage Range 4.5 5.5 V
VIO I/O Level-Shifting Voltage Range 2.8 5.5
IOH(RXD) RXD terminal HIGH level output current –2 mA
IOL(RXD) RXD terminal LOW level output current 2

7.4 Thermal Information

THERMAL METRIC(1) TEST CONDITIONS TCAN1051-Q1 UNIT
D (SOIC) DRB (VSON)
8 Pins 8 Pins
RθJA Junction-to-air thermal resistance High-K thermal resistance(2) 105.8 40.2 °C/W
RθJB Junction-to-board thermal resistance(3) 46.8 49.7 °C/W
RθJC(TOP) Junction-to-case (top) thermal resistance(4) 48.3 15.7 °C/W
ΨJT Junction-to-top characterization parameter(5) 8.7 0.6 °C/W
ΨJB Junction-to-board characterization parameter(6) 46.2 15.9 °C/W
TTSD Thermal shutdown temperature 170 170 °C
TTSD_HYS Thermal shutdown hysteresis 5 5 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

7.5 Power Rating

PARAMETER TEST CONDITIONS POWER DISSIPATION UNIT
PD Average power dissipation VCC = 5 V, VIO = 5 V (if applicable), TJ = 27°C, RL = 60 Ω, S at 0 V, Input to TXD at 250 kHz, CL_RXD = 15 pF. Typical CAN operating conditions at 500 kbps with 25% transmission (dominant) rate. 52 mW
VCC = 5.5 V, VIO = 5.5 V (if applicable), TJ = 150°C, RL = 50 Ω, S at 0 V, Input to TXD at 500 kHz, CL_RXD = 15 pF.  Typical high load CAN operating conditions at 1 Mbps with 50% transmission (dominant) rate and loaded network. 124 mW

7.6 Electrical Characteristics

Over recommended operating conditions, TA = –55°C to 125°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
SUPPLY CHARACTERISTICS
ICC 5-V Supply current Normal mode (dominant) See Figure 5, TXD = 0 V, RL = 60 Ω, CL = open, RCM = open, S = 0V 40 70 mA
See Figure 5, TXD = 0 V, RL = 50 Ω, CL = open, RCM = open, S = 0V 45 80
Normal mode (dominant – bus fault) See Figure 5, TXD = 0 V, S = 0V, CANH = -12V, RL = open, CL = open, RCM = open 180
Normal mode (recessive) See Figure 5, TXD = VCC, RL = 50 Ω, CL = open, RCM = open,
S = 0V		 1.5 2.5
Silent mode See Figure 5, TXD = VCC, RL = 50 Ω,CL = open, RCM = open,
S = VCC 		1.5 2.5
IIO I/O supply current Normal and Silent modes RXD Floating, TXD = S = 0 or 5.5 V 90 300 µA
UVVCC Rising undervoltage detection on VCC for protected mode All devices 4.2 4.4 V
Falling undervoltage detection on VCC for protected mode 3.8 4.0 4.25
VHYS(UVVCC) Hysteresis voltage on UVVCC 200 mV
UVVIO Undervoltage detection on VIO for protected mode Devices with the "V" Suffix (I/O level-shifting) 1.3 2.75 V
VHYS(UVVIO) Hysteresis voltage on UVVIO for protected mode 80 mV
S TERMINAL (MODE SELECT INPUT)
VIH High-level input voltage Devices with the "V" suffix (I/O level-shifting) 0.7 x VIO V
Devices without the "V" suffix (5-V only) 2
VIL Low-level input voltage Devices with the "V" suffix (I/O level-shifting) 0.3 x VIO
Devices without the "V" suffix (5-V only) 0.8
IIH High-level input leakage current S = VCC or VIO = 5.5 V 30 µA
IIL Low-level input leakage current S = 0 V, VCC = VIO = 5.5 V –2 0 2
Ilkg(OFF) Unpowered leakage current S = 5.5 V, VCC = VIO = 0 V -1 1
TXD TERMINAL (CAN TRANSMIT DATA INPUT)
VIH High-level input voltage Devices with the "V" suffix (I/O level-shifting) 0.7 x VIO V
Devices without the "V" suffix (5-V only) 2
VIL Low-level input voltage Devices with the "V" suffix (I/O level-shifting) 0.3 x VIO
Devices without the "V" suffix (5-V only) 0.8
IIH High-level input leakage current TXD = VCC = VIO = 5.5 V –2.5 0 1 µA
IIL Low-level input leakage current TXD = 0 V, VCC = VIO = 5.5 V –100 -25 –7
Ilkg(OFF) Unpowered leakage current TXD = 5.5 V, VCC = VIO = 0 V –1 0 1
CI Input capacitance VIN = 0.4 * sin(4E6 * π * t) + 2.5 V 5 pF
RXD TERMINAL (CAN RECEIVE DATA OUTPUT)
VOH High-level output voltage Devices with the "V" suffix (I/O level-shifting), See Figure 6, IO = –2 mA 0.8 × VIO V
Devices without the "V" suffix (5-V only), See Figure 6, IO = –2 mA 4 4.6
VOL Low-level output voltage Devices with the "V" suffix (I/O level-shifting), See Figure 6, IO = +2 mA 0.2 x VIO
Devices without the "V" suffix (5-V only), See Figure 6, IO = +2 mA 0.2 0.4
Ilkg(OFF) Unpowered leakage current RXD = 5.5 V, VCC = 0 V, VIO = 0 V –1 0 1 µA
DRIVER ELECTRICAL CHARACTERISTICS
VO(DOM) Bus output voltage (dominant CANH See Figure 13 and Figure 5, TXD = 0 V, S = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open 2.75 4.5 V
CANL 0.5 2.25
VO(REC) Bus output voltage (recessive) CANH and CANL See Figure 13 and Figure 5, TXD = VCC, VIO = VCC, S = VCC or 0 V (2), RL = open (no load), RCM = open 2 0.5 × VCC 3
VOD(DOM) Differential output voltage (dominant) CANH - CANL See Figure 13 and Figure 5, TXD = 0 V, S = 0 V, 45 Ω ≤ RL < 50 Ω, CL = open, RCM = open 1.4 3
See Figure 13 and Figure 5, TXD = 0 V, S = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open 1.5 3
See Figure 13 and Figure 5, TXD = 0 V, S = 0 V, RL = 2240 Ω, CL = open, RCM = open 1.5 5
VOD(REC) Differential output voltage (recessive) CANH - CANL See Figure 13 and Figure 5, TXD = VCC, S = 0 V, RL = 60 Ω, CL = open, RCM = open –120 12 mV
See Figure 13 and Figure 5, TXD = VCC, S = 0 V, RL = open (no load), CL = open, RCM = open –50 50
VSYM Transient symmetry (dominant or recessive)
( VO(CANH) + VO(CANL)) / VCC 		See Figure 5 and Figure 15, S at 0 V, Rterm = 60 Ω, Csplit = 4.7 nF, CL = open,
RCM = open, TXD = 250 kHz, 1 MHz		 0.9 1.1 V/V
VSYM_DC DC Output symmetry (dominant or recessive)
(VCC – VO(CANH) – VO(CANL))		 See Figure 5 and , S = 0 V,
RL = 60 Ω, CL = open, RCM = open		 –0.4 0.4 V
IOS(SS_DOM) Short-circuit steady-state output current, dominant See Figure 13 and Figure 11, Figure 11, S at 0 V, VCANH = -5 V to 40 V, CANH = open,
TXD = 0 V		 –100 mA
See Figure 13 and Figure 11, S at 0 V, VCANL = -5 V to 40 V, CANH = open,
TXD = 0 V		 100
IOS(SS_REC) Short-circuit steady-state output current, recessive See Figure 13 and Figure 11, –27 V ≤ VBUS ≤ 32 V, Where VBUS = CANH = CANL, TXD = VCC, all modes –5 5 mA
RECEIVER ELECTRICAL CHARACTERISTICS
VCM Common mode range, normal mode See Figure 6, Table 6 and Table 1, S = 0 or VCC or VIO -30 +30 V
VIT+ Positive-going input threshold voltage, all modes See Figure 6, Table 6 and Table 1, S = 0 or VCC or VIO, -20 V ≤ VCM ≤ +20 V 900 mV
VIT– Negative-going input threshold voltage, all modes 500
VIT+ Positive-going input threshold voltage, all modes See Figure 6, Table 6 and Table 1, S = 0 or VCC or VIO, -30 V ≤ VCM ≤ +30 V 1000
VIT– Negative-going input threshold voltage, all modes 400
VHYS Hysteresis voltage (VIT+ - VIT–) See Figure 6, Table 6 and Table 1, S = 0 or VCC or VIO 120 mV
Ilkg(IOFF) Power-off (unpowered) bus input leakage current CANH = CANL = 5 V, VCC = VIO = 0 V 4.8 µA
CI Input capacitance to ground (CANH or CANL) TXD = VCC, VIO = VCC 24 30 pF
CID Differential input capacitance TXD = VCC, VIO = VCC 12 15 pF
RID Differential input resistance TXD = VCC = VIO = 5 V, S = 0 V,
-30 V ≤ VCM ≤ +30 V		 30 80 kΩ
RIN Input resistance (CANH or CANL) 15 40 kΩ
RIN(M) Input resistance matching:
[1 – RIN(CANH) / RIN(CANL)] × 100%		 VCANH = VCANL = 5 V –2% +2%
(1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 5 V, RL = 60 Ω.
(2) For the bus output voltage (recessive) will be the same if the device is in Normal mode with S terminal LOW or if the device is in Silent mode with the S terminal is HIGH.

7.7 Switching Characteristics

Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
DEVICE SWITCHING CHARACTERISTICS
tPROP(LOOP1) Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant See Figure 8, S = 0 V,
RL = 60 Ω,
CL = 100 pF, CL(RXD) = 15 pF		 100 160 ns
tPROP(LOOP2) Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive 110 175
tMODE Mode change time, from Normal to Silent or from Silent to Normal See Figure 7 1 10 µs
DRIVER SWITCHING CHARACTERISTICS
tpHR Propagation delay time, high TXD to driver recessive (dominant to recessive) See Figure 5, S = 0 V,
RL = 60 Ω,
CL = 100 pF, RCM = open		 75 ns
tpLD Propagation delay time, low TXD to driver dominant (recessive to dominant) 55
tsk(p) Pulse skew (|tpHR - tpLD|) 20
tR Differential output signal rise time 45
tF Differential output signal fall time 45
tTXD_DTO Dominant timeout See Figure 10, S = 0 V,
RL = 60 Ω, CL = open		 1.2 3.8 ms
RECEIVER SWITCHING CHARACTERISTICS
tpRH Propagation delay time, bus recessive input to high output (Dominant to Recessive) See Figure 6, S = 0 V,
CL(RXD) = 15 pF		 65 ns
tpDL Propagation delay time, bus dominant input to low output (Recessive to Dominant) 50 ns
tR RXD Output signal rise time 10 ns
tF RXD Output signal fall time 10 ns
FD Timing Parameters
tBIT(BUS) Bit time on CAN bus output pins with tBIT(TXD) = 500 ns, all devices See Figure 9 , S = 0 V,
RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF,
ΔtREC = tBIT(RXD) - tBIT(BUS) 		435 530 ns
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns, G device variants only 155 210
tBIT(RXD) Bit time on RXD output pins with tBIT(TXD) = 500 ns, all devices 400 550
Bit time on RXD output pins with tBIT(TXD) = 200 ns, G device variants only 120 220
ΔtREC Receiver timing symmetry with tBIT(TXD) = 500 ns, all devices -65 40
Receiver timing symmetry with tBIT(TXD) = 200 ns, G device variants only -45 15

7.8 Typical Characteristics

TCAN1051-Q1 TCAN1051V-Q1 TCAN1051H-Q1 TCAN1051HV-Q1 TCAN1051G-Q1 TCAN1051GV-Q1 TCAN1051HG-Q1 TCAN1051HGV-Q1 D001_SLLSES7.gif
VCC = 5 V VIO = 3.3 V RL = 60 Ω
CL = Open RCM = Open S = 0 V
Figure 1. VOD(D) over Temperature
TCAN1051-Q1 TCAN1051V-Q1 TCAN1051H-Q1 TCAN1051HV-Q1 TCAN1051G-Q1 TCAN1051GV-Q1 TCAN1051HG-Q1 TCAN1051HGV-Q1 D003_SLLSES7.gif
VCC = 5 V VIO = 3.3 V RL = 60 Ω
CL = Open RCM = Open S = 0 V
Figure 3. ICC Recessive over Temperature
TCAN1051-Q1 TCAN1051V-Q1 TCAN1051H-Q1 TCAN1051HV-Q1 TCAN1051G-Q1 TCAN1051GV-Q1 TCAN1051HG-Q1 TCAN1051HGV-Q1 D002_SLLSES7.gif
VIO = 5 V S = 0 V RL = 60 Ω
CL = Open RCM = Open Temp = 25°C
Figure 2. VOD(D) over VCC
TCAN1051-Q1 TCAN1051V-Q1 TCAN1051H-Q1 TCAN1051HV-Q1 TCAN1051G-Q1 TCAN1051GV-Q1 TCAN1051HG-Q1 TCAN1051HGV-Q1 D004_SLLSES7.gif
VCC = 5 V VIO = 3.3 V RL = 60 Ω
CL = 100 pF CL_RXD = 15 pF S = 0 V
Figure 4. Total Loop Delay over Temperature