Refer to the PDF data sheet for device specific package drawings
The processor contains two separate DDR3 EMIFs. This specification covers one of these EMIFs (ddr1_*) and, thus, needs to be implemented twice, once for each EMIF. The PCB layout generally turns out to be a semi-mirror with ddr2_* being a flipped version of ddr1_*; the only exception being the DDR3 devices themselves are not flipped unless mounted on opposite sides of the PCB. Requirements are identical between the two EMIFs.