SPRS951F December   2015  – May 2019 TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2SA , TDA2SG , TDA2SX

PRODUCTION DATA.  

  1. Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. Revision History
  3. Device Comparison
    1. 3.1 Related Products
  4. Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Port (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  External Memory Interface (EMIF)
      5. 4.4.5  General-Purpose Memory Controller (GPMC)
      6. 4.4.6  Timers
      7. 4.4.7  Inter-Integrated Circuit Interface (I2C)
      8. 4.4.8  Universal Asynchronous Receiver Transmitter (UART)
      9. 4.4.9  Multichannel Serial Peripheral Interface (McSPI)
      10. 4.4.10 Quad Serial Peripheral Interface (QSPI)
      11. 4.4.11 Multichannel Audio Serial Port (McASP)
      12. 4.4.12 Universal Serial Bus (USB)
      13. 4.4.13 SATA
      14. 4.4.14 Peripheral Component Interconnect Express (PCIe)
      15. 4.4.15 Controller Area Network Interface (DCAN)
      16. 4.4.16 Ethernet Interface (GMAC_SW)
      17. 4.4.17 eMMC/SD/SDIO
      18. 4.4.18 General-Purpose Interface (GPIO)
      19. 4.4.19 Pulse Width Modulation (PWM) Interface
      20. 4.4.20 System and Miscellaneous
        1. 4.4.20.1 Sysboot Interface
        2. 4.4.20.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.20.3 Real Time Clock (RTC) Interface
        4. 4.4.20.4 System Direct Memory Access (SDMA)
        5. 4.4.20.5 Interrupt Controllers (INTC)
        6. 4.4.20.6 Observability
        7. 4.4.20.7 Power Supplies
      21. 4.4.21 Test Interfaces
  5. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  BC1833IHHV Buffers DC Electrical Characteristics
      8. 5.7.8  USBPHY DC Electrical Characteristics
      9. 5.7.9  Dual Voltage SDIO1833 DC Electrical Characteristics
      10. 5.7.10 Dual Voltage LVCMOS DC Electrical Characteristics
      11. 5.7.11 SATAPHY DC Electrical Characteristics
      12. 5.7.12 PCIEPHY DC Electrical Characteristics
    8. 5.8 Thermal Resistance Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
    2. 6.2 RC On-die Oscillator Clock
    3. 6.3 DPLLs, DLLs Specifications
      1. 6.3.1 DPLL Characteristics
      2. 6.3.2 DLL Characteristics
      3. 6.3.3 DPLL and DLL Noise Isolation
  7. Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem – Video Output Ports
    8. 7.8  Display Subsystem – High-Definition Multimedia Interface (HDMI)
    9. 7.9  External Memory Interface (EMIF)
    10. 7.10 General-Purpose Memory Controller (GPMC)
      1. 7.10.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.10.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.10.3 GPMC/NAND Flash Interface Asynchronous Timing
    11. 7.11 Timers
    12. 7.12 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-34 Timing Requirements for I2C Input Timings
      2. Table 7-35 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
      3. Table 7-36 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    13. 7.13 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-37 Timing Requirements for UART
      2. Table 7-38 Switching Characteristics Over Recommended Operating Conditions for UART
    14. 7.14 Multichannel Serial Peripheral Interface (McSPI)
    15. 7.15 Quad Serial Peripheral Interface (QSPI)
    16. 7.16 Multichannel Audio Serial Port (McASP)
      1. Table 7-45 Timing Requirements for McASP1
      2. Table 7-46 Timing Requirements for McASP2
      3. Table 7-47 Timing Requirements for McASP3/4/5/6/7/8
      4. Table 7-48 Switching Characteristics Over Recommended Operating Conditions for McASP1
      5. Table 7-49 Switching Characteristics Over Recommended Operating Conditions for McASP2
      6. Table 7-50 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
    17. 7.17 Universal Serial Bus (USB)
      1. 7.17.1 USB1 DRD PHY
      2. 7.17.2 USB2 PHY
      3. 7.17.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
    18. 7.18 Serial Advanced Technology Attachment (SATA)
    19. 7.19 Peripheral Component Interconnect Express (PCIe)
    20. 7.20 Controller Area Network Interface (DCAN)
      1. Table 7-65 Timing Requirements for DCANx Receive
      2. Table 7-66 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
    21. 7.21 Ethernet Interface (GMAC_SW)
      1. 7.21.1 GMAC MII Timings
        1. Table 7-67 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-68 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-69 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-70 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.21.2 GMAC MDIO Interface Timings
      3. 7.21.3 GMAC RMII Timings
        1. Table 7-75 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-76 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-77 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-78 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.21.4 GMAC RGMII Timings
        1. Table 7-82 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-83 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-84 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-85 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    22. 7.22 eMMC/SD/SDIO
      1. 7.22.1 MMC1—SD Card Interface
        1. 7.22.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.22.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.22.1.3 SDR12, 4-bit data, half-cycle
        4. 7.22.1.4 SDR25, 4-bit data, half-cycle
        5. 7.22.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.22.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.22.1.7 UHS-I DDR50, 4-bit data
      2. 7.22.2 MMC2 — eMMC
        1. 7.22.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.22.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.22.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
        4. 7.22.2.4 High-speed JC64 DDR, 8-bit data
      3. 7.22.3 MMC3 and MMC4—SDIO/SD
        1. 7.22.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.22.3.2 MMC3 and MMC4, SD High Speed
        3. 7.22.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.22.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.22.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    23. 7.23 General-Purpose Interface (GPIO)
    24. 7.24 System and Miscellaneous interfaces
    25. 7.25 Test Interfaces
      1. 7.25.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.25.1.1 JTAG Electrical Data/Timing
          1. Table 7-134 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-135 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-136 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-137 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.25.2 Trace Port Interface Unit (TPIU)
        1. 7.25.2.1 TPIU PLL DDR Mode
  8. Applications, Implementation, and Layout
    1. 8.1 Introduction
      1. 8.1.1 Initial Requirements and Guidelines
    2. 8.2 Power Optimizations
      1. 8.2.1 Step 1: PCB Stack-up
      2. 8.2.2 Step 2: Physical Placement
      3. 8.2.3 Step 3: Static Analysis
        1. 8.2.3.1 PDN Resistance and IR Drop
      4. 8.2.4 Step 4: Frequency Analysis
      5. 8.2.5 System ESD Generic Guidelines
        1. 8.2.5.1 System ESD Generic PCB Guideline
        2. 8.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 8.2.6 EMI / EMC Issues Prevention
        1. 8.2.6.1 Signal Bandwidth
        2. 8.2.6.2 Signal Routing
          1. 8.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 8.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 8.2.6.3 Ground Guidelines
          1. 8.2.6.3.1 PCB Outer Layers
          2. 8.2.6.3.2 Metallic Frames
          3. 8.2.6.3.3 Connectors
          4. 8.2.6.3.4 Guard Ring on PCB Edges
          5. 8.2.6.3.5 Analog and Digital Ground
    3. 8.3 Core Power Domains
      1. 8.3.1 General Constraints and Theory
      2. 8.3.2 Voltage Decoupling
      3. 8.3.3 Static PDN Analysis
      4. 8.3.4 Dynamic PDN Analysis
      5. 8.3.5 Power Supply Mapping
      6. 8.3.6 DPLL Voltage Requirement
      7. 8.3.7 Loss of Input Power Event
      8. 8.3.8 Example PCB Design
        1. 8.3.8.1 Example Stack-up
        2. 8.3.8.2 vdd_mpu Example Analysis
    4. 8.4 Single-Ended Interfaces
      1. 8.4.1 General Routing Guidelines
      2. 8.4.2 QSPI Board Design and Layout Guidelines
    5. 8.5 Differential Interfaces
      1. 8.5.1 General Routing Guidelines
      2. 8.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 8.5.2.1 Background
        2. 8.5.2.2 USB PHY Layout Guide
          1. 8.5.2.2.1 General Routing and Placement
          2. 8.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 8.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 8.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 8.5.2.2.2.3  Board Stackup
            4. 8.5.2.2.2.4  Cable Connector Socket
            5. 8.5.2.2.2.5  Clock Routings
            6. 8.5.2.2.2.6  Crystals/Oscillator
            7. 8.5.2.2.2.7  DP/DM Trace
            8. 8.5.2.2.2.8  DP/DM Vias
            9. 8.5.2.2.2.9  Image Planes
            10. 8.5.2.2.2.10 JTAG Interface
            11. 8.5.2.2.2.11 Power Regulators
        3. 8.5.2.3 Electrostatic Discharge (ESD)
          1. 8.5.2.3.1 IEC ESD Stressing Test
            1. 8.5.2.3.1.1 Test Mode
            2. 8.5.2.3.1.2 Air Discharge Mode
            3. 8.5.2.3.1.3 Test Type
          2. 8.5.2.3.2 TI Component Level IEC ESD Test
          3. 8.5.2.3.3 Construction of a Custom USB Connector
          4. 8.5.2.3.4 ESD Protection System Design Consideration
        4. 8.5.2.4 References
      3. 8.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 8.5.3.1 USB 3.0 interface introduction
        2. 8.5.3.2 USB 3.0 General routing rules
      4. 8.5.4 HDMI Board Design and Layout Guidelines
        1. 8.5.4.1 HDMI Interface Schematic
        2. 8.5.4.2 TMDS General Routing Guidelines
        3. 8.5.4.3 TPD5S115
        4. 8.5.4.4 HDMI ESD Protection Device (Required)
        5. 8.5.4.5 PCB Stackup Specifications
        6. 8.5.4.6 Grounding
      5. 8.5.5 SATA Board Design and Layout Guidelines
        1. 8.5.5.1 SATA Interface Schematic
        2. 8.5.5.2 Compatible SATA Components and Modes
        3. 8.5.5.3 PCB Stackup Specifications
        4. 8.5.5.4 Routing Specifications
      6. 8.5.6 PCIe Board Design and Layout Guidelines
        1. 8.5.6.1 PCIe Connections and Interface Compliance
          1. 8.5.6.1.1 Coupling Capacitors
          2. 8.5.6.1.2 Polarity Inversion
        2. 8.5.6.2 Non-standard PCIe connections
          1. 8.5.6.2.1 PCB Stackup Specifications
          2. 8.5.6.2.2 Routing Specifications
            1. 8.5.6.2.2.1 Impedance
            2. 8.5.6.2.2.2 Differential Coupling
            3. 8.5.6.2.2.3 Pair Length Matching
        3. 8.5.6.3 LJCB_REFN/P Connections
    6. 8.6 Clock Routing Guidelines
      1. 8.6.1 32-kHz Oscillator Routing
      2. 8.6.2 Oscillator Ground Connection
    7. 8.7 DDR2/DDR3 Board Design and Layout Guidelines
      1. 8.7.1 DDR2/DDR3 General Board Layout Guidelines
      2. 8.7.2 DDR2 Board Design and Layout Guidelines
        1. 8.7.2.1 Board Designs
        2. 8.7.2.2 DDR2 Interface
          1. 8.7.2.2.1  DDR2 Interface Schematic
          2. 8.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 8.7.2.2.3  PCB Stackup
          4. 8.7.2.2.4  Placement
          5. 8.7.2.2.5  DDR2 Keepout Region
          6. 8.7.2.2.6  Bulk Bypass Capacitors
          7. 8.7.2.2.7  High-Speed Bypass Capacitors
          8. 8.7.2.2.8  Net Classes
          9. 8.7.2.2.9  DDR2 Signal Termination
          10. 8.7.2.2.10 VREF Routing
        3. 8.7.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 8.7.3 DDR3 Board Design and Layout Guidelines
        1. 8.7.3.1  Board Designs
          1. 8.7.3.1.1 DDR3 versus DDR2
        2. 8.7.3.2  DDR3 EMIFs
        3. 8.7.3.3  DDR3 Device Combinations
        4. 8.7.3.4  DDR3 Interface Schematic
          1. 8.7.3.4.1 32-Bit DDR3 Interface
          2. 8.7.3.4.2 16-Bit DDR3 Interface
        5. 8.7.3.5  Compatible JEDEC DDR3 Devices
        6. 8.7.3.6  PCB Stackup
        7. 8.7.3.7  Placement
        8. 8.7.3.8  DDR3 Keepout Region
        9. 8.7.3.9  Bulk Bypass Capacitors
        10. 8.7.3.10 High-Speed Bypass Capacitors
          1. 8.7.3.10.1 Return Current Bypass Capacitors
        11. 8.7.3.11 Net Classes
        12. 8.7.3.12 DDR3 Signal Termination
        13. 8.7.3.13 VREF_DDR Routing
        14. 8.7.3.14 VTT
        15. 8.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.7.3.15.1 Four DDR3 Devices
            1. 8.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.7.3.15.2 Two DDR3 Devices
            1. 8.7.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.7.3.15.3 One DDR3 Device
            1. 8.7.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.7.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.7.3.16 Data Topologies and Routing Definition
          1. 8.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.7.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.7.3.17 Routing Specification
          1. 8.7.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.7.3.17.2 DQS and DQ Routing Specification
  9. Device and Documentation Support
    1. 9.1 Device Nomenclature and Orderable Information
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Related Links
    5. 9.5 Community Resources
    6. 9.6 Trademarks
    7. 9.7 Electrostatic Discharge Caution
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ABC|760
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Supply Sequences

This section describes the power-up and power-down sequence required to ensure proper device operation. The power supply names described in this section comprise a superset of a family of compatible devices. Some members of this family will not include a subset of these power supplies and their associated device modules. Refer to Section 4.2, Ball Characteristics for a specific device to determine which power supplies are applicable.

NOTE

For more information, see Power, Reset and Clock Management / Reset Management Functional Description / Reset Sequences of the Device TRM.

Figure 5-2 and Figure 5-3 describe the device Power Sequencing.

TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF SPRS85v_ELCH_01.gifFigure 5-2 Recommended Power-Up Sequencing
  1. Time stamps:
    • T0 = 0 ms; T1 = 0.55 ms; T2 = 1.1 ms; T3 = 1.65 ms; T4 = 2.2 ms; T5 = 2.75 ms; T6 = 3.3 ms; T7 = 5.85 ms; T8 = 6.4 ms; T9 = 8.4 ms. All “Tn” markers show total elapsed time from T0.
  2. Terminology:
    • VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance per Section 5.4, Recommended Operating Conditions.
    • Ramp Up = transition time from VOFF to VOPR MIN.
  3. General timing diagram items:
    • Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
    • Dashed horizontal lines are not valid ramp times but show alternate transition times based upon common sources and clarified in associated note.
    • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power sequencer circuit performance.
  4. vddshv5, vdd_rtc, and vdda_rtc domains:
    • If RTC mode is used, then vdda_rtc, vdd_rtc and vddshv5 must be individually powered with separate power supplies and cannot be combined with other rails.
    • If RTC-mode is not supported then the following combinations are approved:
      • vdda_rtc can be combined with vdds18v
      • vdd_rtc can be combined with vdd
      • vddshv5 can be combined with other 1.8 V or 3.3 V vddshvn rails
      If combinations listed above are not followed then sequencing for these 3 voltage rails should follow the RTC mode timing requirements.
  5. vdda_* rails should not be combined with vdds18v_* for best performance to avoid transient switching noise impacts on analog domains. vdda_* should not ramp-up before vdds18v_* but could ramp concurrently if design ensures final operational voltage will not be reached until after vdds18v. The preferred sequence is to follow all vdds18v_* to ensure circuit components and PCB design do not cause an inadvertent violation.
  6. vdds_ddr* should not ramp-up before vdds18v_*. The preferred sequence has vdds_ddr1 following vdds18v_* to ensure circuit components and PCB design do not cause an inadvertent violation. vdds_ddr1 can ramp-up before, concurrently or after vdda_*, there are no dependencies between vdds_ddr1 and vdda_* domains:
    • For DDR2 mode of operation (1.8 V), vdds_ddr1 supplies can be combined with all vdds18v_* supplies and ramped up together for simplified PDN and power sequencing.
    • If vdds_ddr1 is combined with vdds18v_ddr1 but kept separate from vdds18v on board, then this combined 1.8 V DDR supply can come up together or after the vdds18v supply. The 1.8 V DDR supply should never ramp up before the vdds18v.
  7. vdd should not ramp-up before vdds18v_* or vdds_ddr* domains have reached VOPR MIN.
  8. vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains should follow vdd core supply as preferred sequence. If vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains ramp concurrently or quicker than vdd core, then vdd core must remain at least 150 mV greater than vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains during ramp. Circuit design (components and PCB) must ensure vdd reaches final operational voltage before any of the vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve domains.
  9. VDDA_PHY group should not be combined with VDDA_PLL group to avoid transient switching noise impacts.
  10. vddshv[1-4, 6, 7, 9-11] domains:
    • If 1.8 V I/O signaling is needed, then 1.8 V must be sourced from common vdds18v supply and ramp up concurrently with vdds18v.
    • If 3.3 V I/O signaling is needed, then 3.3 V vddshvx rails must ramp up after vdd_mpu, vdd_iva, vdd_gpu, vdd_dspeve, and VDDA_PHY group domains.
  11. vdda33v_usb[1-2] domain:
    • If USB1 and USB2 interfaces are used, should be supplied from independent analog supply.
    • If USB1/USB2 interface is not used, could be connected to VSS/GND if both conditions are met:
      • USB1/USB2 diff pair (usb1_dm/usb1_dp; usb2_dm/usb2_dp) pins are left unconnected
      • vdda_usb1 and/or vdda_usb2 PHY is not energized
  12. vddshv8 shows two ramp up options for 1.8 V I/O or 3.3 V I/O or SD Card operation:
    • If 1.8 V I/O signaling is needed, then vddshv8 must ramp up after vdd and before or concurrently with 3.3 V vddshv* rails.
    • If 3.3 V I/O signaling is needed, then vddshv8 must be combined with other 3.3 V vddshv* rails.
    • If SD Card operation is needed, then vddshv8 must be sourced from a dual voltage (3.3 V / 1.8 V) power source per SDIO specifications and ramp up concurrently with 3.3 V vddshv* rails.
  13. Pulse duration: rtc_porz must remain low 1 ms after vdda_rtc, vddshv5, and vdd_rtc are ramped and stable or can be de-asserted before but no later than porz. The FUNK_32K_CLK source must be stable and at a valid frequency 1 ms prior to de-asserting rtc_porz high.
  14. porz must remain asserted low until both of the following conditions are met:
    • Minimum of 12 × P, where P = 1 / (SYS_CLK1 / 610), units in ns.
    • All device supply rails reach stable operational levels.
  15. Setup time: sysboot[15:0] pins must be valid 2P(14) before porz is de-asserted high.
  16. Hold time: sysboot[15:0] pins must be valid 15P(14) after porz is de-asserted high.
  17. rstoutn will be set high after global reset, due to porz, is de-asserted following an internal 2 ms delay. rstoutn is only valid after vddshv3 reaches an operational level. If used as a peripheral component reset, it should be AND gated with porz to avoid possible reset glitches during power up.
TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF SPRS85v_ELCH_02.gifFigure 5-3 Recommended Power-Down Sequencing
  1. Time stamps:
    • T0 = 0 ms, T1 > 100 μs, T2 = 0.5 ms, T3 = 1.0 ms, T4 = 1.5 ms; V1 = 2.7 V. All “Tn” markers are intended to show elapsed times from T0. Delta time: Δ TD1 > 100 μs.
  2. Terminology:
    • VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance per Section 5.4, Recommended Operating Conditions.
    • VOFF = OFF Voltage level is defined to be less than 0.6 V where any current draw has no impact to POH.
    • Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.
  3. General timing diagram items:
    • Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
    • Dashed horizontal lines are not valid ramp times but show alternate transition times based upon common sources and clarified in associated note.
    • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit performance.
  4. porz signals must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
  5. vddshv* domains supplied by 3.3 V:
    • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 µs min after porz is asserted low.
    • must be in first group of supplies ramping down after porz has been asserted low for 100 µs min.
    • must not exceed vdds18v by more than 2 V during ramp down, see Figure 5-7 “vdds18v and vdda_* Discharge Relationship”.
  6. vddshv* domains supplied by 1.8 V:
    • must ramp down concurrently with vdds18v and be sourced from the same vdds18v supply.
  7. vddshv8 domain:
    • must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.
    • if SDIO operation is needed, must be sourced from independent power resource that can provide dual voltage (3.3 V / 1.8 V) operation as required to be compliant to SDIO specification
    • if SDIO operation is not needed, must be grouped and ramped down with other vddshv* domains as noted above.
  8. RTC domains (vddshv5, vdd_rtc, and vdda_rtc):
    • If RTC mode is used:
      • rtc_porz can be asserted low before porz and RTC domains can be ramped down after 100 µs elapsed time.
      • must be sourced from independent supplies and must not be combined with other rails.
      • timing diagram shows this mode of operation.
    • If RTC mode is not used, then:
      • rtc_porz must be connected to porz signal.
      • vddshv5 must be grouped and ramped down with other vddshv* domains as noted above.
      • vdd_rtc must be grouped and ramped down with vdd.
      • vdda_rtc must be grouped and ramped down with either VDDA_PHY group or vdds18v.
  9. vdda_* domains:
    • should not be combined with vdds18v for best performance to avoid transient switching noise impacts on analog domains.
    • can ramp down before or concurrently with vdds18v.
    • must satisfy the vdds18v and vdda_* Discharge Relationship (see Figure 5-7) if vdda_* disable point is later or discharge rate is slower than vdds18v.
    • can ramp down before, concurrently or after vdds_ddr*, there is no dependency between these supplies.
  10. vdda33v_usb* domains:
    • can start ramping down 100 µs after low assertion of porz
    • can ramp down concurrently or before VDDA_PHY group
  11. vdd_dspeve, vdd_gpu, vdd_iva, vdd_mpu domains can ramp down before or concurrently with vdd.
  12. vdd can ramp down concurrently or after with vdd_dspeve, vdd_gpu, vdd_iva, vdd_mpu domains.
  13. vdds_ddr* domains:
    • should ramp down after vdd begins ramping down.
    • If DDR2 memory is used (requiring 1.8 V supply):
      • then vdds_ddr* can be combined with vdds18v and vdds18v_ddr* domains and sourced from a common supply. Accordingly, all domains can ramp down concurrently with vdds18v
      • if vdds_ddr* and vdds18v_ddr* are combined but kept separate from vdds18v, then the combined 1.8 V DDR supply can ramp down before or concurrently with vdds18v
  14. vdds18v domain:
    • should maintain VOPR MIN (VNOM -5% = 1.71 V) until all other supplies start to ramp down.
    • must satisfy the vdds18v versus vddshv[1-7, 9-11] Discharge Relationship (see Figure 5-5) if vddshv* is operating at 3.3 V
    • must satisfy the vdds18v and vdds_ddr* Discharge Relationship (see Figure 5-6) if vdds_ddr* discharge rate is slower than vdds18v.

Figure 5-4 describes the RTC-mode Power Sequencing.

TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF SPRS85v_ELCH_03.gifFigure 5-4 RTC Mode Sequencing
  1. Grey shaded areas are windows where it is valid to ramp the voltage rail.
  2. Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
  3. vdd must ramp down after or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
  4. vdd_mpu, vdd_gpu, vdd_dspeve, vdd_iva can be ramped at the same time or can be staggered.
  5. vdd must ramp up before or at the same time as vdd_mpu, vdd_gpu, vdd_dspeve and vdd_iva.
  6. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v.
  7. vddshv8 is separated out to show support for dual voltage. If single voltage is used then vddshv8 can be combined with other vddshvn rails but vddshv8 must ramp down before vdd and must ramp up after vdd.
  8. If any of the vddshv[1-7,9-11] rails (not including vddshv8) are used as 1.8V only, then these rails can be combined with vdds18v. vddshv[1-7,9-11] is allowed to ramp down at either of the two points shown in the timing diagram in either 1.8V mode or in 3.3V mode. If vddshv[1-7,9-11] ramps down at the later time in the diagram then the board design must ensure that the vddshvn rail is never higher than 2.0 V above the vdds18v rail.
  9. vddshv8 is separated out to show support for dual voltage. If a dedicated LDO/supply source is used for vddshv8, then vddshv8 ramp down should occur at one of the two earliest points in the timing diagram. If vddshv8 is powered by the same supply source as the other vddshvn rails, then it is allowed to ramp down at either of the last two points in the timing diagram.

Figure 5-5 describes vddshv[1-7,9-11] Supplies Falling Before vdds18v Supplies Delta.

TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF SPRS85v_ELCH_04.gifFigure 5-5 vdds18v versus vddshv[1-7, 9-11] Discharge Relationship
  1. Vdelta MAX = 2V
  2. If vddshv8 is powered by the same supply source as the other vddshv[1-7,9-11] rails.

If vdds18v and vdds_ddr* are disabled at the same time due to a loss of input power event or if vdds_ddr* discharges more slowly than vdds18v, analysis has shown no reliability impacts when the elapsed time period beginning with vdds18v dropping below 1.0 V and ending with vdds_ddr* dropping below 0.6 V is less than 10 ms (Figure 5-6).

TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF SPRS85v_ELCH_05.gifFigure 5-6 vdds18v and vdds_ddr* Discharge Relationship(1)
  1. V1 > 1.0 V; V2 < 0.6V; T1 < 10ms.
TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF SPRS85v_ELCH_06.gifFigure 5-7 vdds18v and vdda_* Discharge Relationship(3)
  1. vdda_* can be ≥ vdds18v, until vdds18v drops below 1.62 V.
  2. vdds18v must be ≥ vdda_*, until vdds18v reaches 0.6 V.
  3. V1 = 1.62 V; V2 < 0.6 V.

Figure 5-5 through Figure 5-8 and associated notes described the device abrupt power down sequence.

A ”loss of input power event” occurs when the system’s input power is unexpectedly removed. Normally, the recommended power-down sequence should be followed and can be accomplished within 1.5-2 ms of elapsed time. This is the typical range of elapsed time available following a loss of power event, see Section 8.3.7 for design recommendations. If sufficient elapse time is not provided, then an “abrupt” power down sequence can be supported without impacting POH reliability if all of the following conditions are met (Figure 5-8).

TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF SPRS85v_ELCH_07.gifFigure 5-8 Abrupt Power-Down Sequencing(1)
  1. Time stamps:
    • V1 = 2.7 V; V2 = 3.3 V; V3 = 2.0 V; V4 = V5 = V6 = 0.6 V; V7 = V8 = 1.62 V; V9 = 1.3 V; V10 = 1.0 V; V11 = 0.0 V; Tdelta1 > 100 µs; Tdelta2 < 10 ms.
  2. Terminology:
    • VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4, Recommended Operating Conditions table.
    • VOFF = OFF Voltage level is defined to be less than 0.6 V, where any current draw has no impact to POH.
    • Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.
  3. General timing diagram items:
    • Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
    • Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit performance.
  4. porz and rtc_porz must be asserted low for 100 μs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
    • Only if using RTC-mode with an independent RTC input power source, then rtc_porz can remain high and RTC-domains (vdd_rtc, vdda_rtc, and vddshv5) can remain energized while all other domains sourced from the system input power are powered down.
  5. vddshv[1-7, 9-11] domains supplied by 3.3 V:
    • must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 μs min, after porz is asserted low.
    • must not exceed vdds18v voltage level by more than 2 V during ramp down, until vdds18v drops below VOFF (0.6 V).
  6. vddshv[1-7, 9-11] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v supply.
  7. vddshv8 supporting SD Card:
    • must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.
    • must be sourced from independent power resource that can provide dual voltage (3.3 V / 1.8 V) operation as required to be compliant to SDIO specification.
    • if SDIO operation is not needed, must be grouped with other vddshv[1-7, 9-11] domains.
  8. vdda33v_usb[1-2] domains must be in first group of supplies to ramp down after porz has been asserted low for 100 µs min.
  9. vdd_dspeve, vdd_gpu, vdd_iva, vdd_mpu, vdd, vdd_rtc, vdds_ddr1, vdda_* domains can all start to ramp down in any order after 100 µs low assertion of porz.
  10. vdds_ddr1 domains:
    • can remain at VOPR MIN or a level greater than vdds18v during ramp down.
    • elapsed time from vdds18v dropping below 1.0 V to vdds_ddr[1-3] dropping below 0.6 V must not exceed 10 ms.
  11. vdda_* domains:
    • can start to ramp down before or concurrently with vdds18v.
    • must not exceed vdds18v voltage level after vdds18v drops below 1.62 V until vdds18v drops below VOFF (0.6 V).
  12. vdds18v domain should maintain a minimum level of 1.62 V (VNOM – 10%) until vdd_dspeve and vdd start to ramp down.