SPRS996F March 2017 – February 2019 TDA2P-ACD
PRODUCTION DATA.
Table 5-125 and Table 5-126 present Timing requirements and Switching characteristics for MMC1 - DDR50 in receiver and transmitter mode (see Figure 5-82 and Figure 5-83).
NO. | PARAMETER | DESCRIPTION | MODE | MIN | MAX | UNIT |
---|---|---|---|---|---|---|
DDR505 | tsu(cmdV-clk) | Setup time, mmc1_cmd valid before mmc1_clk transition | 1.79 | ns | ||
DDR506 | th(clk-cmdV) | Hold time, mmc1_cmd valid after mmc1_clk transition | 1.6 | ns | ||
DDR507 | tsu(dV-clk) | Setup time, mmc1_dat[3:0] valid before mmc1_clk transition | 1.79 | ns | ||
DDR508 | th(clk-dV) | Hold time, mmc1_dat[3:0] valid after mmc1_clk transition | 1.6 | ns |
NO. | PARAMETER | DESCRIPTION | MIN | MAX | UNIT |
---|---|---|---|---|---|
DDR500 | fop(clk) | Operating frequency, mmc1_clk | 48 | MHz | |
DDR501 | tw(clkH) | Pulse duration, mmc1_clk high | 0.5P-0.185 (1) | ns | |
DDR502 | tw(clkL) | Pulse duration, mmc1_clk low | 0.5P-0.185 (1) | ns | |
DDR503 | td(clk-cmdV) | Delay time, mmc1_clk transition to mmc1_cmd transition | 1.225 | 6.6 | ns |
DDR504 | td(clk-dV) | Delay time, mmc1_clk transition to mmc1_dat[3:0] transition | 1.225 | 6.6 | ns |
NOTE
To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in Table 4-29 and described in Device TRM, Control Module Chapter.
Virtual IO Timings Modes must be used to guarantee some IO timings for MMC1. See Table 5-28, Modes Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See Table 5-127, Virtual Functions Mapping for MMC1 for a definition of the Virtual modes.
Table 5-127 presents the values for DELAYMODE bitfield.
BALL | BALL NAME | Delay Mode Value | MUXMODE[15:0] | ||||
---|---|---|---|---|---|---|---|
MMC1_
VIRTUAL1 |
MMC1_
VIRTUAL2 |
MMC1_
VIRTUAL5 |
MMC1_
VIRTUAL6 |
MMC1_
VIRTUAL7 |
0 | ||
W3 | mmc1_clk | 11 | 10 | 7 | 6 | 5 | mmc1_clk |
W5 | mmc1_cmd | 11 | 10 | 7 | 6 | 5 | mmc1_cmd |
V5 | mmc1_dat0 | 11 | 10 | 7 | 6 | 5 | mmc1_dat0 |
Y4 | mmc1_dat1 | 11 | 10 | 7 | 6 | 5 | mmc1_dat1 |
Y5 | mmc1_dat2 | 11 | 10 | 7 | 6 | 5 | mmc1_dat2 |
Y3 | mmc1_dat3 | 11 | 10 | 7 | 6 | 5 | mmc1_dat3 |
NOTE
To configure the desired Manual IO Timing Mode the user must follow the steps described in section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more information, see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guarantee some IO timings for MMC1. See Table 5-28, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-128, Manual Functions Mapping for MMC1 for a definition of the Manual modes.
Table 5-128 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
BALL | BALL NAME | MMC1_DDR_MANUAL1 | MMC1_SDR104_MANUAL1 | CFG REGISTER | MUXMODE | ||
---|---|---|---|---|---|---|---|
A_DELAY (ps) | G_DELAY (ps) | A_DELAY (ps) | G_DELAY (ps) | 0 | |||
W3 | mmc1_clk | 489 | 0 | - | - | CFG_MMC1_CLK_IN | mmc1_clk |
W5 | mmc1_cmd | 0 | 0 | - | - | CFG_MMC1_CMD_IN | mmc1_cmd |
V5 | mmc1_dat0 | 374 | 0 | - | - | CFG_MMC1_DAT0_IN | mmc1_dat0 |
Y4 | mmc1_dat1 | 31 | 0 | - | - | CFG_MMC1_DAT1_IN | mmc1_dat1 |
Y5 | mmc1_dat2 | 56 | 0 | - | - | CFG_MMC1_DAT2_IN | mmc1_dat2 |
Y3 | mmc1_dat3 | 0 | 0 | - | - | CFG_MMC1_DAT3_IN | mmc1_dat3 |
W3 | mmc1_clk | 1355 | 0 | 892 | 0 | CFG_MMC1_CLK_OUT | mmc1_clk |
W5 | mmc1_cmd | 0 | 0 | 0 | 0 | CFG_MMC1_CMD_OEN | mmc1_cmd |
W5 | mmc1_cmd | 0 | 0 | 0 | 0 | CFG_MMC1_CMD_OUT | mmc1_cmd |
V5 | mmc1_dat0 | 0 | 0 | 0 | 0 | CFG_MMC1_DAT0_OEN | mmc1_dat0 |
V5 | mmc1_dat0 | 0 | 4 | 0 | 0 | CFG_MMC1_DAT0_OUT | mmc1_dat0 |
Y4 | mmc1_dat1 | 0 | 0 | 0 | 0 | CFG_MMC1_DAT1_OEN | mmc1_dat1 |
Y4 | mmc1_dat1 | 0 | 0 | 0 | 0 | CFG_MMC1_DAT1_OUT | mmc1_dat1 |
Y5 | mmc1_dat2 | 0 | 0 | 0 | 0 | CFG_MMC1_DAT2_OEN | mmc1_dat2 |
Y5 | mmc1_dat2 | 0 | 0 | 0 | 0 | CFG_MMC1_DAT2_OUT | mmc1_dat2 |
Y3 | mmc1_dat3 | 0 | 0 | 0 | 0 | CFG_MMC1_DAT3_OEN | mmc1_dat3 |
Y3 | mmc1_dat3 | 0 | 0 | 0 | 0 | CFG_MMC1_DAT3_OUT | mmc1_dat3 |