SNLS697A April 2021 – February 2023 TDES954
PRODUCTION DATA
RX port specific register. The V3Link Port Select register 0x4C configures which unique RX port registers can be accessed by I2C read and write commands.
BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
---|---|---|---|---|
7 | RESERVED | R/W | 0x0 | Reserved |
6 | IE_LINE_LEN_CHG | R/W | 0x0 | Interrupt on Video Line length When enabled, an interrupt is generated if the length of the video line changes. Status is reported in the LINE_LEN_CHG bit in the RX_PORT_STS2 register. |
5 | IE_LINE_CNT_CHG | R/W | 0x0 | Interrupt on Video Line count When enabled, an interrupt is generated if the number of video lines per frame changes. Status is reported in the LINE_CNT_CHG bit in the RX_PORT_STS2 register. |
4 | IE_BUFFER_ERR | R/W | 0x0 | Interrupt on Receiver Buffer Error When enabled, an interrupt is generated if the Receive Buffer overflow is detected as reported in the BUFFER_ERROR bit in the RX_PORT_STS2 register. |
3 | IE_CSI_RX_ERR | R/W | 0x0 | Interrupt on CSI Receiver Error. When enabled, an interrupt will be generated on detection of an error by the CSI Receiver. CSI Receiver errors are reported in the CSI_RX_STS register (address 0x7A). |
2 | IE_V3LINK_PAR_ERR | R/W | 0x0 | Interrupt on V3Link Receiver Parity Error When enabled, an interrupt is generated on detection of parity errors on the V3Link interface for the receive port. Parity error status is reported in the PARITY_ERROR bit in the RX_PORT_STS1 register. |
1 | IE_PORT_PASS | R/W | 0x0 | Interrupt on change in Port PASS status When enabled, an interrupt is generated on a change in receiver port valid status as reported in the PORT_PASS bit in the PORT_STS1 register. |
0 | IE_LOCK_STS | R/W | 0x0 | Interrupt on change in Lock Status When enabled, an interrupt is generated on a change in lock status. Status is reported in the LOCK_STS_CHG bit in the RX_PORT_STS1 register. |