SNLS698A April   2021  – September 2023 TDES960

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  CSI-2 Timing Specifications
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1  CSI-2 Mode
      2. 7.4.2  RAW Mode
      3. 7.4.3  MODE Pin
      4. 7.4.4  REFCLK
      5. 7.4.5  Receiver Port Control
        1. 7.4.5.1 Video Stream Forwarding
      6. 7.4.6  Input Jitter Tolerance
      7. 7.4.7  Adaptive Equalizer
        1. 7.4.7.1 Channel Requirements
        2. 7.4.7.2 Adaptive Equalizer Algorithm
        3. 7.4.7.3 AEQ Settings
          1. 7.4.7.3.1 AEQ Start-Up and Initialization
          2. 7.4.7.3.2 AEQ Range
          3. 7.4.7.3.3 AEQ Timing
          4. 7.4.7.3.4 AEQ Threshold
      8. 7.4.8  Channel Monitor Loop-Through Output Driver
        1. 7.4.8.1 Code Example for CMLOUT V3LINK RX Port 0:
      9. 7.4.9  RX Port Status
        1. 7.4.9.1 RX Parity Status
        2. 7.4.9.2 V3Link Decoder Status
        3. 7.4.9.3 RX Port Input Signal Detection
        4. 7.4.9.4 Line Counter
        5. 7.4.9.5 Line Length
      10. 7.4.10 Sensor Status
      11. 7.4.11 GPIO Support
        1. 7.4.11.1 GPIO Input Control and Status
        2. 7.4.11.2 GPIO Output Pin Control
        3. 7.4.11.3 Forward Channel GPIO
        4. 7.4.11.4 Back Channel GPIO
        5. 7.4.11.5 GPIO Pin Status
        6. 7.4.11.6 Other GPIO Pin Controls
      12. 7.4.12 RAW Mode LV / FV Controls
      13. 7.4.13 CSI-2 Protocol Layer
      14. 7.4.14 CSI-2 Short Packet
      15. 7.4.15 CSI-2 Long Packet
      16. 7.4.16 CSI-2 Data Identifier
      17. 7.4.17 Virtual Channel and Context
      18. 7.4.18 CSI-2 Mode Virtual Channel Mapping
        1. 7.4.18.1 Example 1
        2. 7.4.18.2 Example 2
      19. 7.4.19 CSI-2 Transmitter Frequency
      20. 7.4.20 CSI-2 Output Bandwidth
        1. 7.4.20.1 CSI-2 Output Bandwidth Calculation Example
      21. 7.4.21 CSI-2 Transmitter Status
      22. 7.4.22 Video Buffers
      23. 7.4.23 CSI-2 Line Count and Line Length
      24. 7.4.24 FrameSync Operation
        1. 7.4.24.1 External FrameSync Control
        2. 7.4.24.2 Internally Generated FrameSync
          1. 7.4.24.2.1 Code Example for Internally Generated FrameSync
      25. 7.4.25 CSI-2 Forwarding
        1. 7.4.25.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 7.4.25.2 Synchronized CSI-2 Forwarding
        3. 7.4.25.3 Basic Synchronized CSI-2 Forwarding
          1. 7.4.25.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 7.4.25.4 Line-Interleaved CSI-2 Forwarding
          1. 7.4.25.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 7.4.25.5 Line-Concatenated CSI-2 Forwarding
          1. 7.4.25.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 7.4.25.6 CSI-2 Replicate Mode
        7. 7.4.25.7 CSI-2 Transmitter Output Control
        8. 7.4.25.8 Enabling and Disabling CSI-2 Transmitters
    5. 7.5 Programming
      1. 7.5.1  Serial Control Bus
      2. 7.5.2  Second I2C Port
      3. 7.5.3  I2C Target Operation
      4. 7.5.4  Remote Target Operation
      5. 7.5.5  Remote Target Addressing
      6. 7.5.6  Broadcast Write to Remote Devices
        1. 7.5.6.1 Code Example for Broadcast Write
      7. 7.5.7  I2C Controller Proxy
      8. 7.5.8  I2C Controller Proxy Timing
        1. 7.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 7.5.9  Interrupt Support
        1. 7.5.9.1 Code Example to Enable Interrupts
        2. 7.5.9.2 V3Link Receive Port Interrupts
        3. 7.5.9.3 Interrupts on Forward Channel GPIO
        4. 7.5.9.4 Interrupts on Change in Sensor Status
        5. 7.5.9.5 Code Example to Readback Interrupts
        6. 7.5.9.6 CSI-2 Transmit Port Interrupts
      10. 7.5.10 Error Handling
        1. 7.5.10.1 Receive Frame Threshold
        2. 7.5.10.2 Port PASS Control
      11. 7.5.11 Timestamp – Video Skew Detection
      12. 7.5.12 Pattern Generation
        1. 7.5.12.1 Reference Color Bar Pattern
        2. 7.5.12.2 Fixed Color Patterns
        3. 7.5.12.3 Pattern Generator Programming
          1. 7.5.12.3.1 Determining Color Bar Size
        4. 7.5.12.4 Code Example for Pattern Generator
      13. 7.5.13 V3Link BIST Mode
        1. 7.5.13.1 BIST Operation
    6. 7.6 Register Maps
      1. 7.6.1 Main Registers
      2. 7.6.2 Indirect Access Registers
        1. 7.6.2.1 PATGEN_And_CSI-2 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Over Coax
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
      1. 8.4.1 VDD Power Supply
      2. 8.4.2 Power-Up Sequencing
        1. 8.4.2.1 PDB Pin
        2. 8.4.2.2 System Initialization
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground
        2. 8.5.1.2 Routing V3Link Signal Traces and PoC Filter
        3. 8.5.1.3 CSI-2 Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 DC Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER TEST CONDITIONS PIN OR FREQUENCY MIN TYP MAX UNIT
POWER CONSUMPTION
PT Total power consumption in operation mode CSI-2 TX = 4 data lanes + 1 CLK lane
CSI-2 TX line rate = 1.664 Gbps
4 × V3Link RX inputs
V3Link line rate = 4.16 Gbps
CSI-2 mode, Non-replicate mode, Default registers		 VDD18, VDD11, VDDIO 800 999 mW
SUPPLY CURRENT
IDDT1 Deserializer supply current (includes load current) CSI-2 TX = 4 data lanes + 1 CLK lane
CSI-2 TX line rate = 1.664 Gbps
4 × V3Link RX inputs
V3Link line rate = 4.16 Gbps
CSI-2 mode, Non-replicate mode
Default registers		 VDD11 165 310 mA
VDD18 295 340
VDDIO 2 3
CSI-2 TX = 4 data lanes + 1 CLK lane
CSI-2 TX line rate = 832 Mbps
4 × V3Link RX inputs
V3Link line rate = 4.16 Gbps
CSI-2 mode, Non-replicate mode
Default registers		 VDD11 150 290 mA
VDD18 295 340
VDDIO 2 3
IDDT2 Deserializer supply current (includes load current) CSI-2 TX = 2 x (4 data lanes + 1 CLK lane)
CSI-2 TX line rate = 1.664 Gbps
4 × V3Link RX inputs
V3Link line rate = 4.16 Gbps
CSI-2 mode, Replicate mode
Default registers		 VDD11 174 360 mA

VDD18

312

370

VDDIO

2

3
CSI-2 TX = 2 x (4 data lanes + 1 CLK lane)
CSI-2 TX line rate = 832 Mbps
4 × V3Link RX inputs
V3Link line rate = 4.16 Gbps
CSI-2 mode, Replicate mode
Default registers		 VDD11

127

 305

VDD18

369

415
VDDIO 2 3
IDDT3 Deserializer supply current (includes load current) CSI-2 TX = 4 data lanes + 1 CLK lane
CSI-2 TX line rate = 1.664 Gbps
4 × V3Link RX inputs
V3Link line rate = 1.867 Gbps
RAW12 HF mode, Non-replicate mode
Default registers		 VDD11

122

300

 mA
VDD18

263

305
VDDIO

2

3
CSI-2 TX = 2 x (4 data lanes + 1 CLK lane)
CSI-2 TX line rate = 832 Mbps
4 × V3Link RX inputs
V3Link line rate = 1.867 Gbps
RAW12 HF mode, Replicate mode
Default registers		 VDD11

120

330

 mA
VDD18

315

365
VDDIO

2

3
IDDZ Deserializer shutdown current PDB = LOW VDD11 160 mA
VDD18 4
VDDIO 3
1.8-V LVCMOS I/O
VOH High level output voltage IOH = –2 mA, V(VDDIO) = 1.71 to 1.89 V GPIO[7:0] V(VDDIO) – 0.45 V(VDDIO) V
VOL Low level output voltage IOL = 2 mA, V(VDDIO) = 1.71 to 1.89 V GPIO[7:0], INTB GND 0.45 V
VIH High level input voltage V(VDDIO) = 1.71 to 1.89 V GPIO[7:0], PDB, REFCLK 0.65 ×
V(VDDIO)		 V(VDDIO) V
VIL Low level input voltage GND 0.35 ×
V(VDDIO)
IIH Input high current VIN = V(VDDIO) = 1.71 to 1.89 V, internal pulldown enabled GPIO[7:0], PDB 45 115 μA
VIN = V(VDDIO) = 1.71 to 1.89 V, internal pulldown disabled GPIO[7:0], REFCLK 20 μA
IIL Input low current VIN = 0 V GPIO[7:0], PDB, REFCLK –20 3.5 μA
IIN-STRAP Strap pin input current VIN = 0 V to V(VDD18) MODE, IDX –1 1 μA
IOS Output short circuit current VOUT = 0 V GPIO[7:0] –40 mA
IOZ TRI-STATE output current VOUT = 0 V or V(VDDIO) , PDB = LOW GPIO[7:0] –20 20 μA
3.3-V LVCMOS I/O
VOH High level output voltage IOH = –4 mA, V(VDDIO) = 3.0 to 3.6 V GPIO[7:0] 2.4 V(VDDIO) V
VOL Low level output voltage IOL = 4 mA, V(VDDIO) = 3.0 to 3.6 V GPIO[7:0], INTB GND 0.4 V
VIH High level input voltage V(VDDIO) = 3.0 to 3.6 V GPIO[7:0], REFCLK 2 V(VDDIO) V
PDB 1.17 V(VDDIO) V
VIL Low level input voltage V(VDDIO) = 3.0 to 3.6 V GPIO[7:0], REFCLK GND 0.8 V
PDB GND 0.63 V
IIH Input high current VIN = V(VDDIO) = 3.0 to 3.6 V, internal pulldown enabled GPIO[7:0], PDB 85 215 μA
VIN = V(VDDIO) = 3.0 to 3.6 V, internal pulldown disabled GPIO[7:0], REFCLK 30 μA
IIL Input low current VIN = V(VDDIO) = 0 V GPIO[7:0], PDB, REFCLK –20 3.5 μA
IOS Output short circuit current VOUT = 0 V GPIO[7:0] –65 mA
IOZ TRI-STATE output current VOUT = 0 V or V(VDDIO) , PDB = LOW GPIO[7:0] –20 30 μA
I2C SERIAL CONTROL BUS
VIH Input high level I2C_SDA, I2C_SCL
I2C_SDA2, I2C_SCL2		 0.7 × V(I2C) V(I2C) V
VIL Input low level GND 0.3 × V(I2C) V
VHYS Input hysteresis 50 mV
VOL1 Output low level V(I2C) = 3.0 to 3.6 V, IOL = 3 mA Standard-mode
Fast-mode		 0 0.4 V
V(I2C) = 3.0 to 3.6 V, IOL = 20 mA Fast-mode Plus
VOL2 Output low level V(I2C) = 1.71 to 1.89 V, IOL = 2 mA Fast-mode
Fast-mode Plus		 0 0.2 × V(I2C) V
IIN Input current VIN = 0 V or V(I2C) –10 10 µA
CIN Input capacitance 5 pF
V3LINK RECEIVER INPUT
VCM Common mode voltage RIN0+, RIN0-, RIN1+, RIN1-, RIN2+, RIN2-, RIN3+, RIN3- 1.2 V
RT Internal termination resistance Single-ended RIN+ or RIN- 40 50 60 Ω
Differential across RIN+ and RIN- 80 100 120 Ω
V3LINK BACK CHANNEL DRIVER OUTPUT
VOUT-BC Back channel single-ended output voltage RL = 50 Ω
Coaxial configuration
Forward channel disabled		 RIN0+, RIN1+
RIN2+, RIN3+		 190 220 260 mV
VOD-BC Back channel differential output voltage V(RIN+) - V(RIN-) RL = 100 Ω
STP configuration
Forward channel disabled		 RIN0+, RIN0-, RIN1+, RIN1-, RIN2+, RIN2-, RIN3+, RIN3- 380 440 520 mV
HSTX DRIVER
VCMTX HS transmit static common-mode voltage CSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N, CSI0_CLKP, CSI0_CLKN, CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N, CSI1_CLKP, CSI1_CLKN 150 200 250 mV
|ΔVCMTX(1,0)| VCMTX mismatch when output is 1 or 0 5 mVP-P
|VOD| HS transmit differential voltage 140 200 270 mV
|ΔVOD| VOD mismatch when output is 1 or 0 14 mV
VOHHS HS output high voltage 360 mV
ZOS Single-ended output impedance 40 50 62.5 Ω
ΔZOS Mismatch in single-ended output impedance 10 %
LPTX DRIVER
VOH High level output voltage CSI-2 TX line rate ≤ 1.5 Gbps CSI0_D0P, CSI0_D0N, CSI0_D1P, CSI0_D1N, CSI0_D2P, CSI0_D2N, CSI0_D3P, CSI0_D3N, CSI0_CLKP, CSI0_CLKN, CSI1_D0P, CSI1_D0N, CSI1_D1P, CSI1_D1N, CSI1_D2P, CSI1_D2N, CSI1_D3P, CSI1_D3N, CSI1_CLKP, CSI1_CLKN 1.1 1.2 1.3 V
CSI-2 TX line rate > 1.5 Gbps 0.95 1.3 V
VOL Low level output voltage –50 50 mV
ZOLP Output impedance 110 Ω