SLLSEX2E
December 2016 – July 2022
TDP158
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics, Power Supply
6.6
Electrical Characteristics, Differential Input
6.7
Electrical Characteristics, TMDS Differential Output
6.8
Electrical Characteristics, DDC, I2C, HPD, and ARC
6.9
Electrical Characteristics, TMDS Differential Output in DP-Mode
6.10
Switching Characteristics, TMDS
6.11
Switching Characteristics, HPD
6.12
Switching Characteristics, DDC and I2C
6.13
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Reset Implementation
8.3.2
Operation Timing
8.3.3
Lane Control
8.3.4
Swap
8.3.5
Main Link Inputs
8.3.6
Receiver Equalizer
8.3.7
Input Signal Detect Block
8.3.8
Transmitter Impedance Control
8.3.9
TMDS Outputs
8.3.10
Slew Rate Control
8.3.11
Pre-Emphasis
8.3.12
DP-Mode Description
8.4
Device Functional Modes
8.4.1
DDC Training for HDMI 2.0 Data Rate Monitor
8.4.2
DDC Functional Description
8.5
Register Maps
8.5.1
Local I2C Control BIT Access TAG Convention
8.5.2
BIT Access Tag Conventions
8.5.3
CSR Bit Field Definitions, DEVICE_ID (address = 00h≅07h)
8.5.4
CSR Bit Field Definitions, REV_ID (address = 08h )
8.5.5
CSR Bit Field Definitions – MISC CONTROL 09h (address = 09h)
8.5.6
CSR Bit Field Definitions – MISC CONTROL 0Ah (address = 0Ah)
8.5.7
CSR Bit Field Definitions – MISC CONTROL 0Bh (address = 0Bh)
8.5.8
CSR Bit Field Definitions – MISC CONTROL 0Ch (address = 0Ch)
8.5.9
CSR Bit Field Definitions, Equalization Control Register (address = 0Dh)
8.5.10
CSR Bit Field Definitions, POWER MODE STATUS (address = 20h)
8.5.11
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)
8.5.12
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 31h)
8.5.13
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 32h)
8.5.14
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 33h)
8.5.15
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 34h)
8.5.16
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 35h)
8.5.17
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Dh)
8.5.18
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Eh)
8.5.19
CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Fh)
9
Application and Implementation
9.1
Application Information
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Source Side
9.2.2.2
DDC Pull Up Resistors
9.2.3
Application Curves
9.2.4
Application with DDC Snoop
9.2.4.1
Source Side HDMI Application
9.2.5
9.1.2 Source Side HDMI /DP Application Using DP-Mode
10
Power Supply Recommendations
10.1
Power Management
10.2
Standby Power
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Support Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RSB|40
MPQF185C
Thermal pad, mechanical data (Package|Pins)
RSB|40
QFND255H
Orderable Information
sllsex2e_oa
sllsex2e_pm