SLDS120H March   2000  – March 2022 TFP401 , TFP401A

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Digital I/O Electrical Characteristics
    6. 7.6 DC Electrical Characteristics
    7. 7.7 AC Electrical Characteristics
    8. 7.8 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 TMDS Pixel Data and Control Signal Encoding
      2. 9.3.2 TFP401/401A Clocking and Data Synchronization
      3. 9.3.3 TFP401/401A TMDS Input Levels and Input Impedance Matching
      4. 9.3.4 TFP401A Incorporates HSYNC Jitter Immunity
    4. 9.4 Device Functional Modes
      1. 9.4.1 TFP401/401A Modes of Operation
      2. 9.4.2 TFP401/401A Output Driver Configurations
        1. 9.4.2.1 Output Driver Power Down
        2. 9.4.2.2 Drive Strength
        3. 9.4.2.3 Time-Staggered Pixel Output
        4. 9.4.2.4 Power Management
        5. 9.4.2.5 Sync Detect
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Data and Control Signals
        2. 10.2.2.2 Configuration Options
        3. 10.2.2.3 Power Supplies Decoupling
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Layer Stack
      2. 12.1.2 Routing High-Speed Differential Signal Traces (RxC–, RxC+, Rx0–, Rx0+, Rx1–, Rx1+, Rx2–, Rx2+)
      3. 12.1.3 DVI Connector
    2. 12.2 Layout Example
    3. 12.3 TI PowerPAD 100-TQFP Package
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Support Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

AC Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
VID(2)Differential input sensitivity(1)1501560mVp-p
tpsAnalog input intra-pair (+ to –) differential skew(8)0.4tbit(2)
tccsAnalog input inter-pair or channel-to-channel
skew (8)
1tpix(3)
tijitWorst-case differential input clock jitter tolerance(8)(4)50ps
tf1Fall time of data and control signals(5)(6)ST = low, CL = 5 pF2.4ns
ST = high, CL = 10 pF1.9
tr1Rise time of data and control signals(5)(6)ST = low, CL = 5 pF2.4ns
ST = high, CL = 10 pF1.9
tr2Rise time of ODCK clock(5)ST = low, CL = 5 pF2.4ns
ST = high, CL = 10 pF1.9
tf2Fall time of ODCK clock(5)ST = low, CL = 5 pF2.4ns
ST = high, CL = 10 pF1.9
tsu1Setup time, data and control signal to falling edge of ODCK1 pixel/clock, PIXS = low, OCK_INV = low1.8ns
2 pixel/clock, PIXS = high,
STAG = high, OCK_INV = low
3.8
2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = low0.7
th1Hold time, data and control signal to falling edge of ODCK1 pixel/clock, PIXS = low, OCK_INV = low0.6ns
2 pixel and STAG, PIXS = high,
STAG = low, OCK_INV = low
2.5
2 pixel/clock, PIXS = high,
STAG = high, OCK_INV = low
2.9
tsu2Setup time, data and control signal to rising edge of ODCK1 pixel/clock, PIXS = low,
OCK_INV = high
2.1ns
2 pixel/clock, PIXS = high,
STAG = high, OCK_INV = high
4
2 pixel and STAG, PIXS = high,
STAG = low, OCK_INV = high
1.5
th2Hold time, data and control signal to rising edge of ODCK1 pixel/clock, PIXS = low, OCK_INV = high0.5ns
2 pixel and STAG, PIXS = high,
STAG = low, OCK_INV = high
2.4
2 pixel/clock, PIXS = high,
STAG = high, OCK_INV = high
2.1
fODCKODCK frequencyPIX = low (1-PIX/CLK)25165MHz
PIX = high (2-PIX/CLK)12.582.5
ODCK duty-cycle40%50%60%
tpd(PDL)Propagation delay time from PD low to Hi-Z outputs9ns
tpd(PDOL)Propagation delay time from PDO low to Hi-Z outputs9ns
tt(HSC)Transition time between DE transition to SCDT low(7)1e6tpix
tt(FSC)Transition time between DE transition to SCDT high(7)1600tpix
td(st)Delay time, ODCK latching edge to QE[23:0] data outputSTAG = low, PIXS = high0.25tpix
tWL(PDL_MIN)Minimum time PD is asserted low9ns
tDELMinimum DE low128Tpixel
Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection.
tbit is 1/10 the pixel time, tpix.
tpix is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to tpix in 1-pixel/clock mode or 2tpix when in 2-pixel/clock mode.
Measured differentially at 50% crossing using ODCK output clock as trigger.
Rise and fall times measured as time between 20% and 80% of signal amplitude.
Data and control signals are QE[23:0], QO[23:0], DE, HSYNC, VSYNC. and CTL[3:1].
Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
By characterization.