SLDS190B November   2012  – March 2022 TFP401A-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Digital I/O Electrical Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TMDS Pixel Data and Control Signal Encoding
      2. 7.3.2 TFP401A-Q1 Clocking and Data Synchronization
      3. 7.3.3 TFP401A-Q1 TMDS Input Levels and Input Impedance Matching
      4. 7.3.4 TFP401A-Q1 Device Incorporates HSYNC Jitter Immunity
    4. 7.4 Device Functional Modes
      1. 7.4.1 TFP401A-Q1 Modes of Operation
      2. 7.4.2 TFP401A-Q1 Output Driver Configurations
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Typical Application
        1. 8.1.1.1 Design Requirements
        2. 8.1.1.2 Detailed Design Procedure
          1. 8.1.1.2.1 Data and Control Signals
          2. 8.1.1.2.2 Configuration Options
          3. 8.1.1.2.3 Power Supplies Decoupling
        3. 8.1.1.3 Application Curves
        4. 8.1.1.4 DVDD
        5. 8.1.1.5 OVDD
        6. 8.1.1.6 AVDD
        7. 8.1.1.7 PVDD
    2. 8.2 Power Supply Recommendations
    3. 8.3 Layout
      1. 8.3.1 Layout Guidelines
        1. 8.3.1.1 Layer Stack
        2. 8.3.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)
      2. 8.3.2 Layout Example
      3. 8.3.3 TI PowerPAD 100-TQFP Package
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 3: –40°C to 85°C ambient operating temperature range
    • Device HBM ESD classification level H2
    • Device CDM ESD classification level C3B
  • Supports pixel rates up to 165 MHz (including 1080p and WUXGA at 60 Hz)
  • Digital visual interface (DVI) specification compliant(1)
  • True-Color, 24-bit/pixel, 16.7M colors at 1 or 2 pixels per clock
  • Laser-trimmed internal termination resistors for optimum fixed impedance matching
  • Skew tolerant up to one pixel-clock cycle
  • 4× oversampling
  • Reduced power consumption: 1.8-V core operation with 3.3-V I/Os and supplies(2)
  • Reduced ground bounce using time-staggered pixel outputs
  • Low noise and good power dissipation using TI PowerPAD™ packaging
  • Advanced technology using TI 0.18-µm EPIC-5™ CMOS process
  • TFP401A-Q1 Incorporates HSYNC Jitter Immunity(3)
1. The TFP401A-Q1 device incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on the transmitted HSYNC signal.
2. The TFP401A-Q1 device has an internal voltage regulator that provides the 1.8-V core power supply from the external 3.3-V supplies.
3. The Digital Visual Interface Specification, DVI, is an industry standard developed by the Digital Display Working Group (DDWG) for high-speed digital connection to digital displays. The TFP401A-Q1 is compliant with the DVI Specification Rev. 1.0.