SLDS145C October 2001 – December 2014 TFP410
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TFP401 is a DVI (Digital Visual Interface) compliant digital receiver that is used in digital flat panel display systems to receive and decode T.M.D.S. encoded RGB pixel data streams. In a digital display system a host, usually a PC or workstation, contains a DVI compliant transmitter that receives 24 bit pixel data along with appropriate control signals and encodes them into a high-speed, low voltage differential serial bit stream fit for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, will require a DVI compliant receiver like the TI TFP401 to decode the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive circuitry to produce an image on the display. Because the host and display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred. The TFP401 will support resolutions up to UXGA.
|Power supply||3.3 V dc at 1 A|
|Input clock frequency range||25 MHz — 165 MHz|
|Output format||24 bits/pixel|
|Input clock latching||Rising edge|
|I2C EEPROM support||No|
The trace length of data and control signals out of the receiver should be kept as close to equal as possible. Trace separation should be approximately 5 times the height. As a general rule, traces also should be less than 2.8” if possible (longer traces can be acceptable).
The TFP410 can be configured in several modes depending on the required input format, for example 1 byte/clock, 2 bytes/clock, falling/rinsing clock edge.
Refer to Table 1 for more information about configuration options.
Digital, analog, and PLL supplies must be decoupled from each other to avoid electrical noise on the PLL and the core.
Sometimes the Panel does not support the same format as the GPU (graphics processor unit). In these cases the user must decide how to connect the unused bits.