SLDS145C October   2001  – December 2014 TFP410

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 T.M.D.S. Pixel Data and Control Signal Encoding
      2. 7.3.2 Universal Graphics Controller Interface Voltage Signal Levels
      3. 7.3.3 Universal Graphics Controller Interface Clock Inputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Universal Graphics Controller Interface Modes
      2. 7.4.2 Data De-skew Feature
      3. 7.4.3 Hot Plug/Unplug (Auto Connect/Disconnect Detection)
      4. 7.4.4 Device Configuration and I2C RESET Description
      5. 7.4.5 DE Generator
    5. 7.5 Programming
      1. 7.5.1 I2C interface
    6. 7.6 Register Maps
      1. 7.6.1  VEN_ID Register (Sub-Address = 01−00 ) [reset = 0x014C]
      2. 7.6.2  DEV_ID Register (Sub-Address = 03-02) [reset = 0x0410]
      3. 7.6.3  REV_ID Register (Sub-Address = 04) [reset = 0x00]
      4. 7.6.4  Reserved Register (Sub-Address = 07-05) [reset = 0x641400]
      5. 7.6.5  CTL_1_MODE (Sub-Address = 08) [reset = 0xFE]
      6. 7.6.6  CTL_2_MODE Register (Sub-Address = 09) [reset = 0x00]
      7. 7.6.7  CTL_3_MODE Register (Sub-Address = 0A) [reset = 0x80]
      8. 7.6.8  CFG Register (Sub-Address = 0B)
      9. 7.6.9  RESERVED Register (Sub-Address = 0E-0C) [reset = 0x97D0A9]
      10. 7.6.10 DE_DLY Register (Sub-Address = 32) [reset = 0x00]
      11. 7.6.11 DE_CTL Register (Sub-Address = 33) [reset = 0x00]
      12. 7.6.12 DE_TOP Register (Sub-Address = 34) [reset = 0x00]
      13. 7.6.13 DE_CNT Register (Sub-Address = 37-36) [reset = 0x0000]
      14. 7.6.14 DE_LIN Register (Sub-Address = 39-38) [reset = 0x0000]
      15. 7.6.15 H_RES Register (Sub-Address = 3B−3A)
      16. 7.6.16 V_RES Register (Sub-Address = 3D−3C)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Data and Control Signals
        2. 8.2.2.2 Configuration Options
        3. 8.2.2.3 Power Supplies Decoupling
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 DVDD
    2. 9.2 TVDD
    3. 9.3 PVDD
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layer Stack
      2. 10.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)
      3. 10.1.3 DVI Connector
    2. 10.2 Layout Example
    3. 10.3 TI PowerPAD 64-Pin HTQFP Package
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The TFP410 is a DVI-compliant digital transmitter that is used in digital host monitor systems to T.M.D.S. encode and serialize RGB pixel data streams. TFP410 supports resolutions from VGA to WUXGA (and 1080p) and can be controlled in two ways:

  1. Configuration and state pins
  2. The programmable I2C serial interface (see Table 1)

The host in a digital display system, usually a PC or consumer electronics device, contains a DVI-compatible transmitter such as the TI TFP410 that receives 24-bit pixel data along with appropriate control signals. The TFP410 encodes the signals into a high speed, low voltage, differential serial bit stream optimized for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor, requires a DVI compatible receiver like the TI TFP401 to decode the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat panel drive circuitry to produce an image on the display. Because the host and display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred (see the T.M.D.S. Pixel Data and Control Signal Encoding section, Universal Graphics Controller Interface Voltage Signal Levels section, and Universal Graphics Controller Interface Clock Inputs section).

The TFP410 integrates a high-speed digital interface, a T.M.D.S. encoder, and three differential T.M.D.S. drivers. Data is driven to the TFP410 encoder across 12 or 24 data lines, along with differential clock pair and sync signals. The flexibility of the TFP410 allows for multiple clock and data formats that enhance system performance.

The TFP410 also has enhanced PLL noise immunity, an enhancement accomplished with on-chip regulators and bypass capacitors.

The TFP410 is versatile and highly programmable to provide maximum flexibility for the user. An I2C host interface is provided to allow enhanced configurations in addition to power-on default settings programmed by pin-strapping resistors.

The TFP410 offers monitor detection through receiver detection, or hot-plug detection when I2C is enabled. The monitor detection feature allows the user enhanced flexibility when attaching to digital displays or receivers (see the Hot Plug/Unplug (Auto Connect/Disconnect Detection) section and the Register Maps section).

The TFP410 has a data de-skew feature allowing the users to de-skew the input data with respect to the IDCK± (see the Data De-skew Feature section).

7.2 Functional Block Diagram

fbd_slds145.gif

7.3 Feature Description

7.3.1 T.M.D.S. Pixel Data and Control Signal Encoding

For transition minimized differential signaling (T.M.D.S.), only one of two possible T.M.D.S. characters for a given pixel is transmitted at a given time. The transmitter keeps a running count of the number of ones and zeros previously sent and transmits the character that minimizes the number of transitions and approximates a dc balance of the transmission line. Three T.M.D.S. channels are used to transmit RGB pixel data during the active video interval (DE = High). These same three channels are also used to transmit HSYNC, VSYNC, and three user definable control signals, CTL[3:1], during the inactive display or blanking interval (DE = Low). The following table maps the transmitted output data to the appropriate T.M.D.S. output channel in a DVI-compliant system.

INPUT PINS
(VALID FOR DE = High)
T.M.D.S. OUTPUT CHANNEL TRANSMITTED PIXEL DATA
ACTIVE DISPLAY (DE = High)
DATA[23:16] Channel 2 (TX2 ±) Red[7:0]
DATA[15:8] Channel 1 (TX1 ±) Green[7:0]
DATA[7:0] Channel 0 (TX0 ±) Blue[7:0]
INPUT PINS
(VALID FOR DE = Low)
T.M.D.S. OUTPUT CHANNEL TRANSMITTED CONTROL DATA
BLANKING INTERVAL (DE = Low)
CTL3, CTL2(1) Channel 2 (TX2 ±) CTL[3:2]
CTL1 (1) Channel 1 (TX1 ±) CTL[1]
HSYNC, VSYNC Channel 0 (TX0 ±) HSYNC, VSYNC
(1) The TFP410 encodes and transfers the CTL[3:1] inputs during the vertical blanking interval. The CTL3 input is reserved for HDCP compliant DVI TXs and the CTL[2:1] inputs are reserved for future use. When DE = high, CTL and SYNC pins must be held constant.

7.3.2 Universal Graphics Controller Interface Voltage Signal Levels

The universal graphics controller interface can operate in the following two distinct voltage modes:

  • The high-swing mode where standard 3.3-V CMOS signaling levels are used.
  • The low-swing mode where adjustable 1.1-V to 1.8-V signaling levels are used.

To select the high-swing mode, the VREF input pin must be tied to the 3.3-V power supply.

To select the low-swing mode, the VREF must be 0.55 to 0.95 V.

In the low-swing mode, VREF is used to set the midpoint of the adjustable signaling levels. The allowable range of values for VREF is from 0.55 V to 0.9 V. The typical approach is to provide this from off chip by using a simple voltage-divider circuit. The minimum allowable input signal swing in the low-swing mode is VREF ±0.2 V. In low-swing mode, the VREF input is common to all differential input receivers.

7.3.3 Universal Graphics Controller Interface Clock Inputs

The universal graphics controller interface of the TFP410 supports both fully differential and single-ended clock input modes. In the differential clock input mode, the universal graphics controller interface uses the crossover point between the IDCK+ and IDCK− signals as the timing reference for latching incoming data (DATA[23:0], DE, HSYNC, and VSYNC). Differential clock inputs provide greater common-mode noise rejection. The differential clock input mode is only available in the low-swing mode. In the single-ended clock input mode, the IDCK+ input (Pin 57) should be connected to the single-ended clock source and the IDCK− input (Pin 56) should be tied to GND.

The universal graphics controller interface of the TFP410 provides selectable 12-bit dual-edge, and 24-bit single-edge, input clocking modes. In the 12-bit dual-edge, the 12-bit data is latched on each edge of the input clock. In the 24-bit single-edge mode, the 24-bit data is latched on the rising edge of the input clock when EDGE = 1 and the falling edge of the input clock when EDGE = 0.

DKEN and DK[3:1] allow the user to compensate the skew between IDCK± and the pixel data and control signals. See Table 10 for details.

7.4 Device Functional Modes

7.4.1 Universal Graphics Controller Interface Modes

Table 1 is a tabular representation of the different modes for the universal graphics controller interface. The 12-bit mode is selected when BSEL=0 and the 24-bit mode when BSEL=1. The 12-bit mode uses dual-edge clocking and the 24-bit mode uses single-edge clocking. The EDGE input is used to control the latching edge in 24-bit mode, or the primary latching edge in 12-bit mode. When EDGE=1, the data input is latched on the rising edge of the input clock; and when EDGE=0, the data input is latched on the falling edge of the input clock. A fully differential input clock is available only in the low-swing mode. Single-ended clocking is not recommended in the low-swing mode as this decreases common-mode noise rejection.

Note that BSEL, DSEL, and EDGE are determined by register CTL_1_MODE when I2C is enabled (ISEL=1) and by input pins when I2C is disabled (ISEL=0).

Table 1. Universal Graphics Controller Interface Options (Tabular Representation)

VREF BSEL EDGE DSEL BUS WIDTH LATCH MODE CLOCK EDGE CLOCK MODE
0.55 V − 0.9 V 0 0 0 12-bit Dual-edge Falling Differential(1)(2)
0.55 V − 0.9 V 0 0 1 12-bit Dual-edge Falling Single-ended
0.55 V – 0.9 V 0 1 0 12-bit Dual-edge Rising Differential(1)(2)
0.55 V − 0.9 V 0 1 1 12-bit Dual-edge Rising Single-ended
0.55 V – 0.9 V 1 0 0 24-bit Single-edge Falling Single-ended
0.55 V – 0.9 V 1 0 1 24-bit Single-edge Falling Differential(1)(3)
0.55 V – 0.9 V 1 1 0 24-bit Single-edge Rising Single-ended
0.55 V – 0.9 V 1 1 1 24-bit Single-edge Rising Differential(1)(3)
DVDD 0 0 X 12-bit Dual-edge Falling Single-ended(4)
DVDD 0 1 X 12-bit Dual-edge Rising Single-ended(4)
DVDD 1 0 X 24-bit Single-edge Falling Single-ended(4)
DVDD 1 1 X 24-bit Single-edge Rising Single-ended(4)
(1) The differential clock input mode is only available in the low signal swing mode (that is, VREF ≤ 0.9 V).
(2) The TFP410 does not support a 12-bit dual-clock, single-edge input clocking mode.
(3) The TFP410 does not support a 24-bit single-clock, dual-edge input clocking mode.
(4) In the high-swing mode (VREF = DVDD), DSEL is a don’t care; therefore, the device is always in the single-ended latch mode.
td_universal_grpc_12_bit_slds145.gifFigure 7. Universal Graphics Controller Interface Options for 12-Bit Mode (Graphical Representation)
td_universal_grpc_24_bit_slds145.gifFigure 8. Universal Graphics Controller Interface Options for 24-Bit Mode (Graphical Representation)

Table 2. 12-Bit Mode Data Mapping

PIN NAME P0 P1 P2
P0L P0H P1L P1H P2L P2H
LOW HIGH LOW HIGH LOW HIGH
D11 G0[3] R0[7] G1[3] R1[7] G2[3] R2[7]
D10 G0[2] R0[6] G1[2] R1[6] G2[2] R2[6]
D9 G0[1] R0[5] G1[1] R1[5] G2[1] R2[5]
D8 G0[0] R0[4] G1[0] R1[4] G2[0] R2[4]
D7 B0[7] R0[3] B1[7] R1[3] B2[7] R2[3]
D6 B0[6] R0[2] B1[6] R1[2] B2[6] R2[2]
D5 B0[5] R0[1] B1[5] R1[1] B2[5] R2[1]
D4 B0[4] R0[0] B1[4] R1[0] B2[4] R2[0]
D3 B0[3] G0[7] B1[3] G1[7] B2[3] G2[7]
D2 B0[2] G0[6] B1[2] G1[6] B2[2] G2[6]
D1 B0[1] G0[5] B1[1] G1[5] B2[1] G2[5]
D0 B0[0] G0[4] B1[0] G1[4] B2[0] G2[4]

Table 3. 24-Bit Mode Data Mapping

PIN NAME P0 P1 P2 PIN NAME P0 P1 P2
D23 R0[7] R1[7] R2[7] D11 G0[3] G1[3] G2[3]
D22 R0[6] R1[6] R2[6] D10 G0[2] G1[2] G2[2]
D21 R0[5] R1[5] R2[5] D9 G0[1] G1[1] G2[1]
D20 R0[4] R1[4] R2[4] D8 G0[0] G1[0] G2[0]
D19 R0[3] R1[3] R2[3] D7 B0[7] B1[7] B2[7]
D18 R0[2] R1[2] R2[2] D6 B0[6] B1[6] B2[6]
D17 R0[1] R1[1] R2[1] D5 B0[5] B1[5] B2[5]
D16 R0[0] R1[0] R2[0] D4 B0[4] B1[4] B2[4]
D15 G0[7] G1[7] G2[7] D3 B0[3] B1[3] B2[3]
D14 G0[6] G1[6] G2[6] D2 B0[2] B1[2] B2[2]
D13 G0[5] G1[5] G2[5] D1 B0[1] B1[1] B2[1]
D12 G0[4] G1[4] G2[4] D0 B0[0] B1[0] B2[0]

7.4.2 Data De-skew Feature

The de-skew feature allows adjustment of the input setup/hold time. Specifically, the input data DATA[23:0] can be latched slightly before or after the latching edge of the clock IDCK± depending on the amount of de-skew desired. When de-skew enable (DKEN) is enabled, the amount of de-skew is programmable by setting the three bits DK[3:1]. When disabled, a default de-skew setting is used. To allow maximum flexibility and ease of use, DKEN and DK[3:1] are accessed directly through configuration pins when I2C is disabled, or through registers of the same name when I2C is enabled. When using I2C mode, the DKEN pin should be tied to ground to avoid a floating input.

The input setup/hold time can be varied with respect to the input clock by an amount t(CD) given by the formula in Equation 1.

Equation 1. t(CD) = (DK[3:1] – 4) × t(STEP)

where

  • t(STEP) is the adjustment increment amount
  • DK[3:1] is a number from 0 to 7 represented as a 3-bit binary number
  • t(CD) is the cumulative de-skew amount

(DK[3:1]-4) is simply a multiplier in the range \{-4,-3,-2,-1, 0, 1, 2, 3\} for t(STEP). Therefore, data can be latched in increments from 4 times the value of t(STEP) before the latching edge of the clock to 3 times the value of t(STEP) after the latching edge. Note that the input clock is not changed, only the time when data is latched with respect to the clock.

td_grphcl_rep_de_skew_slds145.gifFigure 9. A Graphical Representation of the De-Skew Function

7.4.3 Hot Plug/Unplug (Auto Connect/Disconnect Detection)

TFP410 supports hot plug/unplug (auto connect/disconnect detection) for the DVI link. The receiver sense input (RSEN) bit indicates if a DVI receiver is connected to TXC+ and TXC–. The HTPLG bit reflects the current state of the HTPLG pin connected to the monitor via the DVI connector. When I2C is disabled (ISEL=0), the RSEN value is available on the MSEN pin. When I2C is enabled, the connection status of the DVI link and HTPLG sense pins are provided by the CTL_2_MODE register. The MSEL bits of the CTL_2_MODE register can be used to program the MSEN to output the HTPLG value, the RSEN value, an interrupt, or be disabled.

The source of the interrupt event is selected by TSEL in the CTL_2_MODE register. An interrupt is generated by a change in status of the selected signal. The interrupt status is indicated in the MDI bit of CTL_2_MODE and can be output via the MSEN pin. The interrupt continues to be asserted until a 1 is written to the MDI bit, resetting the bit back to 0. Writing 0 to the MDI bit has no effect.

7.4.4 Device Configuration and I2C RESET Description

The TFP410 device configuration can be programmed by several different methods to allow maximum flexibility for the user’s application. Device configuration is controlled depending on the state of the ISEL/RST pin, configuration pins (BSEL, DSEL, EDGE, VREF) and state pins (PD, DKEN). I2C bus select and I2C RESET (active low) are shared functions on the ISEL/RST pin, which operates asynchronously.

Holding ISEL/RST low causes the device configuration to be set by the configuration pins (BSEL, DSEL, EDGE, and VREF) and state pins (PD, DKEN). The I2C bus is disabled.

Holding ISEL/RST high causes the chip configuration to be set based on the configuration bits (BSEL, DSEL, EDGE) and state bits (PD, DKEN) in the I2C registers. The I2C bus is enabled.

Momentarily bringing ISEL/RST low and then back high while the device is operating in normal or power-down mode will RESET the I2C registers to their default values. The device configuration will be changed to the default power-up state with I2C enabled. After power up, the device must be reset. It is suggested that this pin be tied to the system reset signal, which is low during power up and is then asserted high after all the power supplies are fully functional.

7.4.5 DE Generator

The TFP410 contains a DE generator that can be used to generate an internal DE signal when the original data source does not provide one. There are several I2C programmable values that control the DE generator (see Figure 10). DE_GEN in the DE_CTL register enables this function. When enabled, the DE pin is ignored.

DE_TOP and DE_LIN are line counts used to control the number of lines after VSYNC goes active that DE is enabled, and the total number of lines that DE remains active, respectively. The polarity of VSYNC must be set by VS_POL in the DE_CTL register.

DE_DLY and DE_CNT are pixel counts used to control the number of pixels after HSYNC goes active that DE is enabled, and the total number of pixels that DE remains active, respectively. The polarity of HSYNC must be set by HS_POL in the DE_CTL register.

The TFP410 also counts the total number of HSYNC pulses between VSYNC pulses, and the total number of pixels between HSYNC pulses. These values, the total vertical and horizontal resolutions, are available in V_RES and H_RES, respectively. These values are available at all times, whether or not the DE generator is enabled.

de_gen_reg_func_slds145.gifFigure 10. DE Generator Register Functions

7.5 Programming

7.5.1 I2C interface

The I2C interface is used to access the internal TFP410 registers. This two-pin interface consists of the SCL clock line and the SDA serial data line. The basic I2C access cycles are shown in Figure 11 and Figure 12.

td_i2c_strt_stp_slds145.gifFigure 11. I2C Start and Stop Conditions

The basic access write cycle consists of the following:

  1. A start condition
  2. A slave address cycle
  3. A sub-address cycle
  4. Any number of data cycles
  5. A stop condition

The basic access read cycle consists of the following:

  1. A start condition
  2. A slave write address cycle
  3. A sub-address cycle
  4. A restart condition
  5. A slave read address cycle
  6. Any number of data cycles
  7. A stop condition

The start and stop conditions are shown in Figure 11. The high to low transition of SDA while SCL is high defines the start condition. The low to high transition of SDA while SCL is high defines the stop condition. Each cycle, data or address, consists of 8 bits of serial data followed by one acknowledge bit generated by the receiving device. Thus, each data/address cycle contains 9 bits as shown in Figure 12.

td_i2c_acc_cyc_slds145.gifFigure 12. I2C Access Cycles

Following a start condition, each I2C device decodes the slave address. The TFP410 responds with an acknowledge by pulling the SDA line low during the ninth clock cycle if it decodes the address as its address. During subsequent sub-address and data cycles, the TFP410 responds with acknowledge as shown in Figure 13. The sub-address is auto-incremented after each data cycle.

The transmitting device must not drive the SDA signal during the acknowledge cycle so that the receiving device may drive the SDA signal low. The master indicates a not acknowledge condition (A) by keeping the SDA signal high just before it asserts the stop condition (P). This sequence terminates a read cycle as shown in Figure 14.

The slave address consists of 7 bits of address along with 1 bit of read/write information (read = 1, write = 0) as shown below in Figure 12 and Figure 13. For the TFP410, the selectable slave addresses (including the R/W bit) using A[3:1] are 0x70, 0x72, 0x74, 0x76, 0x78, 0x7A, 0x7C, and 0x7E for write cycles and 0x71, 0x73, 0x75, 0x77, 0x79, 0x7B, 0x7D, and 0x7F for read cycles.

i2c_write_cyc_slds145.gifFigure 13. I2C Write Cycle
i2c_read_cyc_slds145.gifFigure 14. I2C Read Cycle

7.6 Register Maps

The TFP410 is a standard I2C slave device. All the registers can be written and read through the I2C interface (unless otherwise specified). The TFP410 slave machine supports only byte read and write cycles. Page mode is not supported. The 8-bit binary address of the I2C machine is 0111 A3A2A1X, where A[3:1] are pin programmable or set to 000 by default. The I2C base address of the TFP410 is dependent on A[3:1] (pins 6, 7 and 8 respectively) as shown below.

A[3:1] WRITE ADDRESS
(Hex)
READ ADDRESS
(Hex)
000 70 71
001 72 73
010 74 75
011 76 77
100 78 79
101 7A 7B
110 7C 7D
111 7E 7F
REGISTER RW SUB-
ADDRESS
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
VEN_ID R 00 VEN_ID[7:0]
R 01 VEN_ID[15:8]
DEV_ID R 02 DEV_ID[7:0]
R 03 DEV_ID[15:8]
REV_ID R 04 REV_ID[7:0]
RESERVED R 05-07 Reserved
CTL_1_MODE RW 08 RSVD TDIS VEN HEN DSEL BSEL EDGE PD
CTL_2_MODE RW 09 VLOW MSEL TSEL RSEN HTPLG MDI
CTL_3_MODE RW 0A DK DKEN CTL RSVD
CFG RW 0B CFG
RESERVED RW 0C-31 Reserved
DE_DLY RW 32 DE_DLY[7:0]
DE_CTL RW 33 RSVD DE_GEN VS_POL HS_POL RSVD DE_DLY[8]
DE_TOP RW 34 RSVD DE_DLY[6:0]
RESERVED RW 35 Reserved
DE_CNT RW 36 DE_CNT[7:0]
RW 37 Reserved DE_CNT[10:8]
DE_LIN RW 38 DE_LIN[7:0]
RW 39 Reserved DE_LIN[10:8]
H_RES R 3A H_RES[7:0]
R 3B Reserved H_RES[10:8]
V_RES R 3C V_RES[7:0]
R 3D Reserved V_RES[10:8]
RESERVED R 3E−FF

7.6.1 VEN_ID Register (Sub-Address = 01−00 ) [reset = 0x014C]

Figure 15. VEN_ID Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VEN_ID[15:8] VEN_ID[7:0]

Table 4. VEN_ID Field Descriptions

Bit Field Type Description
15:8 VEN_ID R These read-only registers contain the 16-bit Texas Instruments vendor ID. VEN_ID is hardwired to 0x014C.
7:0 VEN_ID R

7.6.2 DEV_ID Register (Sub-Address = 03–02) [reset = 0x0410]

Figure 16. DEV_ID Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DEV_ID[15:8] DEV_ID[7:0]

Table 5. DEV_ID Register Field Descriptions

Bit Field Type Description
15:8 DEV_ID R These read-only registers contain the 16-bit device ID for the TFP410. DEV_ID is hardwired to 0x0410.
7:0 DEV_ID R

7.6.3 REV_ID Register (Sub-Address = 04) [reset = 0x00]

Figure 17. REV_ID Register
7 6 5 4 3 2 1 0
REV_ID[7:0]

Table 6. REV_ID Register Field Descriptions

Bit Field Type Description
7:0 REV_ID R This read-only register contains the revision ID.

7.6.4 Reserved Register (Sub-Address = 07–05) [reset = 0x641400]

Figure 18. Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED[15:8] RESERVED[7:0]

Table 7. Reserved Field Descriptions

Bit Field Type Description
15:8 RESERVED Read Only
7:0 RESERVED Read Only

7.6.5 CTL_1_MODE (Sub-Address = 08) [reset = 0xFE]

Figure 19. CTL_1_MODE Register
7 6 5 4 3 2 1 0
RSVD TDIS VEN HEN DSEL BSEL EDGE PD

Table 8. CTL_1_MODE Field Descriptions

Bit Field Type Description
7 RSVD R/W Reserved
6 TDIS R/W This read/write register contains the T.M.D.S. disable mode
0: T.M.D.S. circuitry enable state is determined by PD.
1: T.M.D.S. circuitry is disabled.
5 VEN R/W This read/write register contains the vertical sync enable mode.
0: VSYNC input is transmitted as a fixed low
1: VSYNC input is transmitted in its original state
4 HEN R/W This read/write register contains the horizontal sync enable mode.
0: HSYNC input is transmitted as a fixed low
1: HSYNC input is transmitted in its original state
3 DSEL R/W This read/write register is used in combination with BSEL and VREF to select the single-ended or differential input clock mode. In the high-swing mode, DSEL is a don’t care because IDCK is always single-ended.
2 BSEL R/W This read/write register contains the input bus select mode.
0: 12-bit operation with dual-edge clock
1: 24-bit operation with single-edge clock
1 EDGE R/W This read/write register contains the edge select mode.
0: Input data latches to the falling edge of IDCK+
1: Input data latches to the rising edge of IDCK+
0 PD R/W This read/write register contains the power-down mode.
0: Power down (default after RESET)
1: Normal operation

7.6.6 CTL_2_MODE Register (Sub-Address = 09) [reset = 0x00]

Figure 20. CTL_2_MODE Register
7 6 5 4 3 2 1 0
VLOW MSEL[3:1] TSEL RSEN HTPLG MDI

Table 9. CTL_2_MODE Field Descriptions

Bit Field Type Description
7 VLOW R/W This read only register indicates the VREF input level.
0: This bit is a logic level (0) if the VREF analog input selects high-swing inputs
1: This bit is a logic level (1) if the VREF analog input selects low-swing inputs
6:4 MSEL[3:1] R/W This read/write register contains the source select of the monitor sense output pin.
000: Disabled. MSEN output high
001: Outputs the MDI bit (interrupt)
010: Outputs the RSEN bit (receiver detect)
011: Outputs the HTPLG bit (hot plug detect)
3 TSEL R/W This read/write register contains the interrupt generation source select.
0: Interrupt bit (MDI) is generated by monitoring RSEN
1: Interrupt bit (MDI) is generated by monitoring HTPLG
2 RSEN R/W This read only register contains the receiver sense input logic state, which is valid only for dc-coupled systems.
0: A powered-on receiver is not detected
1: A powered-on receiver is detected (that is, connected to the DVI transmitter outputs)
1 HTPLG R/W This read only register contains the hot plug detection input logic state.
0: Logic level detected on the EDGE/HTPLG pin (pin 9)
1: High level detected on the EDGE/HTPLG pin (pin 9)
0 MDI R/W This read/write register contains the monitor detect interrupt mode.
0: Detected logic level change in detection signal (to clear, write one to this bit)
1: Logic level remains the same

7.6.7 CTL_3_MODE Register (Sub-Address = 0A) [reset = 0x80]

Figure 21. CTL_3_MODE Register
7 6 5 4 3 2 1 0
DK[3:1] DKEN CTL[3:1] RSVD

Table 10. CTL_3_MODE Register Field Descriptions

Bit Field Type Description
7:5 DK[3:1] RW This read/write register contains the de-skew setting, each increment adjusts the skew by t(STEP).
000: Step 1 (minimum setup/maximum hold)
001: Step 2
010: Step 3
011: Step 4
100: Step 5 (default)
101: Step 6
110: Step 7
111: Step 8 (maximum setup/minimum hold)
4 DKEN RW This read/write register controls the data de-skew enable.
0: Data de-skew is disabled, the values in DK[3:1] are not used
1: Data de-skew is enabled, the de-skew setting is controlled through DK[3:1]
3:1 CTL[3:1] RW This read/write register contains the values of the three CTL[3:1] bits that are output on the DVI port during the blanking interval.
0 RSVD RW

7.6.8 CFG Register (Sub-Address = 0B)

Figure 22. CFG Register
7 6 5 4 3 2 1 0
CFG[7:0]

Table 11. CFG Register Field Descriptions

Bit Field Type Description
7:0 (D[23:16]) CFG Read Only This read-only register contains the state of the inputs D[23:16]. These pins can be used to provide the user with selectable configuration data through the I2C bus.

7.6.9 RESERVED Register (Sub-Address = 0E–0C) [reset = 0x97D0A9]

Figure 23. RESERVED Register
7 6 5 4 3 2 1 0
RESERVED

Table 12. RESERVED Register Field Descriptions

Bit Field Type Description
7:0 RESERVED R/W

7.6.10 DE_DLY Register (Sub-Address = 32) [reset = 0x00]

Figure 24. DE_DLY Register
7 6 5 4 3 2 1 0
DE_DLY[7:0]

Table 13. DE_DLY Field Descriptions

Bit Field Type Description
7:0 DE_DLY R/W This read/write register defines the number of pixels after HSYNC goes active that DE is generated, when the DE generator is enabled.

7.6.11 DE_CTL Register (Sub-Address = 33) [reset = 0x00]

Figure 25. DE_CTL Register
7 6 5 4 3 2 1 0
Reserved DE_GEN VS_POL HS_POL Reserved DE_DLY[8]

Table 14. DE_CTL Register Field Descriptions

Bit Field Type Description
7 Reserved R/W
6 DE_GEN R/W This read/write register enables the internal DE generator.
0: DE generator is disabled. Signal required on DE pin
1: DE generator is enabled. DE pin is ignored.
5 VS_POL R/W This read/write register sets the VSYNC polarity.
0: VSYNC is considered active low.
1: VSYNC is considered active high.
Line counts are reset on the VSYNC active edge.
4 HS_POL R/W This read/write register sets the HSYNC polarity.
0: HSYNC is considered active low.
1: HSYNC is considered active high. Pixel counts are reset on the HSYNC active edge.
1:3 Reserved R/W
0 DE_DLY[8] R/W This read/write register contains the top bit of DE_DLY.

7.6.12 DE_TOP Register (Sub-Address = 34) [reset = 0x00]

Figure 26. DE_TOP Register
7 6 5 4 3 2 1 0
DE_TOP[7:0]

Table 15. DE_TOP Register Field Descriptions

Bit Field Type Description
7:0 DE_TOP R/W This read/write register defines the number of pixels after VSYNC goes active that DE is generated, when the DE generator is enabled.

7.6.13 DE_CNT Register (Sub-Address = 37–36) [reset = 0x0000]

Figure 27. DE_CNT Register
7 6 5 4 3 2 1 0
DE_CNT[7:0]
Reserved DE_CNT[10:8]

Table 16. DE_CNT Register Field Descriptions

Bit Field Type Description
10:8 DE_CNT R/W These read/write registers define the width of the active display, in pixels, when the DE generator is enabled.
7:0 DE_CNT R/W

7.6.14 DE_LIN Register (Sub-Address = 39–38) [reset = 0x0000]

Figure 28. DE_LIN Register
7 6 5 4 3 2 1 0
DE_LIN[7:0]
Reserved DE_LIN[10:8]

Table 17. DE_LIN Register Field Descriptions

Bit Field Type Description
10:8 DE_LIN R/W These read/write registers define the height of the active display, in lines, when the DE generator is enabled.
7:0 DE_LIN R/W

7.6.15 H_RES Register (Sub-Address = 3B−3A)

Figure 29. H_RES Register
7 6 5 4 3 2 1 0
H_RES[7:0]
Reserved H_RES[10:8]

Table 18. H_RES Register Field Descriptions

Bit Field Type Description
10:8 H_RES Read Only These read-only registers return the number of pixels between consecutive HSYNC pulses.
7:0 H_RES Read Only

7.6.16 V_RES Register (Sub-Address = 3D−3C)

Figure 30. V_RES Register
7 6 5 4 3 2 1 0
V_RES[7:0]
Reserved V_RES[10:8]

Table 19. V_RES Register Field Descriptions

Bit Field Type Description
10:8 V_RES Read Only These read-only registers return the number of lines between consecutive VSYNC pulses.
7:0 V_RES Read Only