SLDS145C October   2001  – December 2014 TFP410

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 T.M.D.S. Pixel Data and Control Signal Encoding
      2. 7.3.2 Universal Graphics Controller Interface Voltage Signal Levels
      3. 7.3.3 Universal Graphics Controller Interface Clock Inputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Universal Graphics Controller Interface Modes
      2. 7.4.2 Data De-skew Feature
      3. 7.4.3 Hot Plug/Unplug (Auto Connect/Disconnect Detection)
      4. 7.4.4 Device Configuration and I2C RESET Description
      5. 7.4.5 DE Generator
    5. 7.5 Programming
      1. 7.5.1 I2C interface
    6. 7.6 Register Maps
      1. 7.6.1  VEN_ID Register (Sub-Address = 01−00 ) [reset = 0x014C]
      2. 7.6.2  DEV_ID Register (Sub-Address = 03-02) [reset = 0x0410]
      3. 7.6.3  REV_ID Register (Sub-Address = 04) [reset = 0x00]
      4. 7.6.4  Reserved Register (Sub-Address = 07-05) [reset = 0x641400]
      5. 7.6.5  CTL_1_MODE (Sub-Address = 08) [reset = 0xFE]
      6. 7.6.6  CTL_2_MODE Register (Sub-Address = 09) [reset = 0x00]
      7. 7.6.7  CTL_3_MODE Register (Sub-Address = 0A) [reset = 0x80]
      8. 7.6.8  CFG Register (Sub-Address = 0B)
      9. 7.6.9  RESERVED Register (Sub-Address = 0E-0C) [reset = 0x97D0A9]
      10. 7.6.10 DE_DLY Register (Sub-Address = 32) [reset = 0x00]
      11. 7.6.11 DE_CTL Register (Sub-Address = 33) [reset = 0x00]
      12. 7.6.12 DE_TOP Register (Sub-Address = 34) [reset = 0x00]
      13. 7.6.13 DE_CNT Register (Sub-Address = 37-36) [reset = 0x0000]
      14. 7.6.14 DE_LIN Register (Sub-Address = 39-38) [reset = 0x0000]
      15. 7.6.15 H_RES Register (Sub-Address = 3B−3A)
      16. 7.6.16 V_RES Register (Sub-Address = 3D−3C)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Data and Control Signals
        2. 8.2.2.2 Configuration Options
        3. 8.2.2.3 Power Supplies Decoupling
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 DVDD
    2. 9.2 TVDD
    3. 9.3 PVDD
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layer Stack
      2. 10.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)
      3. 10.1.3 DVI Connector
    2. 10.2 Layout Example
    3. 10.3 TI PowerPAD 64-Pin HTQFP Package
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PAP Package
64 Pin HTQFP
Top View
po_diag_slds145.gif

Pin Functions

PIN TYPE DESCRIPTION
NAME NO.
INPUT
DATA[23:12] 36−47 I The upper 12 bits of the 24-bit pixel bus
In 24-bit, single-edge input mode (BSEL = high), this bus inputs the top half of the 24-bit pixel bus. In 12-bit, dual-edge input mode (BSEL = low), these bits are not used to input pixel data. In this mode, the state of DATA[23:16] is input to the I2C register CFG. This allows 8 bits of user configuration data to be read by the graphics controller through the I2C interface (see the Register Maps section).
Note: All unused data inputs should be tied to GND or VDD.
DATA[11:0] 50−55,
58−63
I The lower 12 bits of the 24-bit pixel bus/12-bit pixel bus input
In 24-bit, single-edge input mode (BSEL = high), this bus inputs the bottom half of the 24-bit pixel bus. In 12-bit, dual-edge input mode (BSEL = low), this bus inputs 1/2 a pixel (12 bits) at every latch edge (both rising and falling) of the clock.
IDCK–
IDCK+
56
57
I Differential clock input. The TFP410 supports both single-ended and fully differential clock input modes. In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the single-ended clock source and the IDCK− input (pin 56) should be tied to GND. In the differential clock input mode, the TFP410 uses the crossover point between the IDCK+ and IDCK– signals as the timing reference for latching incoming data DATA[23:0], DE, HSYNC, and VSYNC. The differential clock input mode is only available in the low signal swing mode.
DE 2 I Data enable. As defined in DVI 1.0 specification, the DE signal allows the transmitter to encode pixel data or control data on any given input clock cycle. During active video (DE = high), the transmitter encodes pixel data, DATA[23:0]. During the blanking interval (DE = low), the transmitter encodes HSYNC, VSYNC and CTL[3:1].
HSYNC 4 I Horizontal sync input
VSYNC 5 I Vertical sync input
CTL3/A3/DK3
CTL2/A2/DK2
CTL1/A1/DK1
6
7
8
I The operation of these three multifunction inputs depends on the settings of the ISEL (pin 13) and DKEN (pin 35) inputs. All three inputs support 3.3-V CMOS signal levels and contain weak pulldown resistors so that if left unconnected they default to all low.
When the I2C bus is disabled (ISEL = low) and the de-skew mode is disabled (DKEN = low), these three inputs become the control inputs, CTL[3:1], which can be used to send additional information across the DVI link during the blanking interval (DE = low). The CTL3 input is reserved for HDCP compliant DVI TXs (TFP510) and the CTL[2:1] inputs are reserved for future use.
When the I2C bus is disabled (ISEL = low) and the de-skew mode is enabled (DKEN = high), these three inputs become the de-skew inputs DK[3:1], used to adjust the setup and hold times of the pixel data inputs DATA[23:0], relative to the clock input IDCK±.
When the I2C bus is enabled (ISEL = high), these three inputs become the 3 LSBs of the I2C slave address, A[3:1].
CONFIGURATION/PROGRAMMING
MSEN/PO1 11 O Monitor sense/programmable output 1. The operation of this pin depends on whether the I2C interface is enabled or disabled. This pin has an open-drain output and is only 3.3-V tolerant. An external 5-kΩ pullup resistor connected to VDD is required on this pin.
When I2C is disabled (ISEL = low), a low level indicates a powered on receiver is detected at the differential outputs. A high level indicates a powered on receiver is not detected. This function is only valid in dc-coupled systems.
When I2C is enabled (ISEL = high), this output is programmable through the I2C interface (see the I2C register descriptions section).
ISEL/RST 13 I I2C interface select/I2C RESET (active low, asynchronous)
If ISEL is high, then the I2C interface is active. Default values for the I2C registers can be found in the Register Maps section.
If ISEL is low, then I2C is disabled and the chip configuration is specified by the configuration pins (BSEL, DSEL, EDGE, VREF) and state pins (PD, DKEN).
If ISEL is brought low and then back high, the I2C state machine is reset. The register values are changed to their default values and are not preserved from before the reset.
BSEL/SCL 15 I Input bus select/I2C clock input. The operation of this pin depends on whether the I2C interface is enabled or disabled. This pin is only 3.3-V tolerant.
When I2C is disabled (ISEL = low), a high level selects 24-bit input, single-edge input mode. A low level selects 12-bit input, dual-edge input mode.
When I2C is enabled (ISEL = high), this pin functions as the I2C clock input (see the Register Maps section). In this configuration, this pin has an open-drain output that requires an external 5-kΩ pullup resistor connected to VDD.
DSEL/SDA 14 I/O DSEL/I2C data. The operation of this pin depends on whether the I2C interface is enabled or disabled. This pin is only 3.3-V tolerant.
When I2C is disabled (ISEL = low), this pin is used with BSEL and VREF to select the single-ended or differential input clock mode (see Table 1).
When I2C is enabled (ISEL = high), this pin functions as the I2C bidirectional data line. In this configuration, this pin has an open-drain output that requires an external 5-kΩ pullup resistor connected to VDD.
EDGE/HTPLG 9 I Edge select/hot plug input. The operation of this pin depends on whether the I2C interface is enabled or disabled. This input is 3.3-V tolerant only.
When I2C is disabled (ISEL = low), a high level selects the primary latch to occur on the rising edge of the input clock IDCK+. A low level selects the primary latch to occur on the falling edge of the input clock IDCK+. This is the case for both single-ended and differential input clock modes.
When I2C is enabled (ISEL = high), this pin is used to monitor the hot plug detect signal. When used for hot-plug detection, this pin requires a series
1-kΩ resistor.
DKEN 35 I Data de-skew enable. The de-skew function can be enabled either through I2C or by this pin when I2C is disabled. When de-skew is enabled, the input clock to data setup/hold time can be adjusted in discrete trim increments. The amount of trim per increment is defined by t(STEP).
When I2C is disabled (ISEL = low), a high level enables de-skew with the trim increment determined by pins DK[3:1] (see the Data De-skew Feature section). A low level disables de-skew and the default trim setting is used.
When I2C is enabled (ISEL = high), the value of DKEN and the trim increment are selected through I2C. In this configuration, the DKEN pin should be tied to either GND or VDD to avoid a floating input.
VREF 3 I Input reference voltage. Selects the swing range of the digital data inputs (DATA[23:0], DE, HSYNC, VSYNC, and IDCK±).
For high-swing 3.3-V input signal levels, VREF should be tied to VDD.
For low-swing input signal levels, VREF should be set to half of the maximum input voltage level. See Recommended Operating Conditions for the allowable range for VREF.
The desired VREF voltage level is typically derived using a simple voltage-divider circuit.
PD 10 I Power down (active low). In the powerdown state, only the digital I/O buffers and I2C interface remain active.
When I2C is disabled (ISEL = low), a high level selects the normal operating mode. A low level selects the powerdown mode.
When I2C is enabled (ISEL = high), the power-down state is selected through I2C. In this configuration, the PD pin should be tied to GND.
Note: The default register value for PD is low, so the device is in powerdown mode when I2C is first enabled or after an I2C RESET.
RESERVED
RESERVED 34 I This pin is reserved and must be tied to GND for normal operation.
DVI DIFFERENTIAL SIGNAL OUTPUT PINS
TX0+
TX0−
25
24
O Channel 0 DVI differential output pair. TX0± transmits the 8-bit blue pixel data during active video andHSYNC and VSYNC during the blanking interval.
TX1+
TX1−
28
27
O Channel 1 DVI differential output pair. TX1± transmits the 8-bit green pixel data during active video and CTL[1] during the blanking interval.
TX2+
TX2−
31
30
O Channel 2 DVI differential output pair. TX2± transmits the 8-bit red pixel data during active video and CTL[3:2] during the blanking interval.
TXC+
TXC−
22
21
O DVI differential output clock.
TFADJ 19 I Full-scale adjust. This pin controls the amplitude of the DVI output voltage swing, determined by the value of the pullup resistor RTFADJ connected to TVDD.
POWER AND GROUND PINS
DVDD 1, 12, 33 Power Digital power supply. Must be set to 3.3 V nominal.
PVDD 18 Power PLL power supply. Must be set to 3.3 V nominal.
TVDD 23, 29 Power Transmitter differential output driver power supply. Must be set to 3.3 V nominal.
DGND 16, 48, 64 Ground Digital ground
PGND 17 Ground PLL ground
TGND 20, 26, 32 Ground Transmitter differential output driver ground
NC 49 NC No connection required. If connected, tie high.