SLDS145C October   2001  – December 2014 TFP410

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 T.M.D.S. Pixel Data and Control Signal Encoding
      2. 7.3.2 Universal Graphics Controller Interface Voltage Signal Levels
      3. 7.3.3 Universal Graphics Controller Interface Clock Inputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Universal Graphics Controller Interface Modes
      2. 7.4.2 Data De-skew Feature
      3. 7.4.3 Hot Plug/Unplug (Auto Connect/Disconnect Detection)
      4. 7.4.4 Device Configuration and I2C RESET Description
      5. 7.4.5 DE Generator
    5. 7.5 Programming
      1. 7.5.1 I2C interface
    6. 7.6 Register Maps
      1. 7.6.1  VEN_ID Register (Sub-Address = 01−00 ) [reset = 0x014C]
      2. 7.6.2  DEV_ID Register (Sub-Address = 03-02) [reset = 0x0410]
      3. 7.6.3  REV_ID Register (Sub-Address = 04) [reset = 0x00]
      4. 7.6.4  Reserved Register (Sub-Address = 07-05) [reset = 0x641400]
      5. 7.6.5  CTL_1_MODE (Sub-Address = 08) [reset = 0xFE]
      6. 7.6.6  CTL_2_MODE Register (Sub-Address = 09) [reset = 0x00]
      7. 7.6.7  CTL_3_MODE Register (Sub-Address = 0A) [reset = 0x80]
      8. 7.6.8  CFG Register (Sub-Address = 0B)
      9. 7.6.9  RESERVED Register (Sub-Address = 0E-0C) [reset = 0x97D0A9]
      10. 7.6.10 DE_DLY Register (Sub-Address = 32) [reset = 0x00]
      11. 7.6.11 DE_CTL Register (Sub-Address = 33) [reset = 0x00]
      12. 7.6.12 DE_TOP Register (Sub-Address = 34) [reset = 0x00]
      13. 7.6.13 DE_CNT Register (Sub-Address = 37-36) [reset = 0x0000]
      14. 7.6.14 DE_LIN Register (Sub-Address = 39-38) [reset = 0x0000]
      15. 7.6.15 H_RES Register (Sub-Address = 3B−3A)
      16. 7.6.16 V_RES Register (Sub-Address = 3D−3C)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Data and Control Signals
        2. 8.2.2.2 Configuration Options
        3. 8.2.2.3 Power Supplies Decoupling
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 DVDD
    2. 9.2 TVDD
    3. 9.3 PVDD
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Layer Stack
      2. 10.1.2 Routing High-Speed Differential Signal Traces (RxC-, RxC+, Rx0-, Rx0+, Rx1-, Rx1+, Rx2-, Rx2+)
      3. 10.1.3 DVI Connector
    2. 10.2 Layout Example
    3. 10.3 TI PowerPAD 64-Pin HTQFP Package
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
DVDD, PVDD, TVDD Supply voltage range –0.5 4 V
Input voltage, logic/analog signals –0.5 4 V
RT External DVI single-ended termination resistance 0 to open circuit Ω
External TFADJ resistance, RTFADJ 300 to open circuit Ω
Case temperature for 10 seconds 260 °C
JEDEC latch-up (EIA/JESD78) 100 mA
Tstg Storage temperature 260 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) DVI pins ±4000 V
All other pins ±2000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage (DVDD, PVDD, TVDD) 3.0 3.3 3.6 V
VREF Input reference voltage Low-swing mode 0.55 VDDQ/2(1) 0.9 V
High-swing mode DVDD V
AVDD DVI termination supply voltage(2) DVI receiver 3.14 3.3 3.46 V
RT DVI Single-ended termination resistance(3) DVI receiver 45 50 55 Ω
R(TFADJ) TFADJ resistor for DVI-compliant V(SWING) range 400 mV = V(SWING) = 600 mV 505 510 515 Ω
TA Operating free-air temperature range 0 25 70 °C
(1) VDDQ defines the maximum low-level input voltage, it is not an actual input voltage.
(2) AVDD is the termination supply voltage of the DVI link.
(3) RT is the single-ended termination resistance at the receiver end of the DVI link.

6.4 Thermal Information

THERMAL METRIC(1) TFP410 UNIT
PAP
64 PINS
RθJA Junction-to-ambient thermal resistance 26.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 14.1
RθJB Junction-to-board thermal resistance 11.3
ψJT Junction-to-top characterization parameter 0.4
ψJB Junction-to-board characterization parameter 11.2
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC SPECIFICATIONS
VIH High-level input voltage (CMOS input) VREF = DVDD 0.7 VDD V
0.5 V ≤ V ≤ 0.95 V VREF + 0.2
VIL Low-level input voltage (CMOS input) VREF = DVDD 0.3VDD V
0.5 V ≤V ≤ 0.95 V VREF – 0.2
VOH High-level digital output voltage (open-drain output) VDD = 3 V, IOH = 20 μA 2.4 V
VOL Low-level digital output voltage (open-drain output) VDD = 3.6 V, IOL = 4 mA 0.4 V
IIH High-level input current VI = 3.6 V ±25 µA
IIL Low-level input current VI = 0 ±25 µA
VH DVI single-ended high-level output voltage AVDD = 3.3 V ± 5%,
RT(1) = 50 Ω ± 10%,
RTFADJ = 510 Ω ± 1%
AVDD – 0.01 AVDD + 0.01 V
VL DVI single-ended low-level output voltage AVDD – 0.6 AVDD – 0.4 V
VSWING DVI single-ended output swing voltage 400 600 mVP-P
VOFF DVI single-ended standby/off output voltage AVDD – 0.01 AVDD + 0.01 V
IPD Power-down current(3) 200 500 µA
IIDD Normal power supply current Worst-case pattern(2) 200 250 mA
AC SPECIFICATIONS
f(IDCK) IDCK frequency 25 165 MHz
tr DVI output rise time (20-80%)(4) f(IDCK) = 165 MHz 75 240 ps
tf DVI output fall time (20-80%)(4) 75 240 ps
tsk(D) DVI output intra-pair + to − differential skew(5), see Figure 4 50 ps
tojit DVI output clock jitter, max.(6) 150 ps
t(STEP) De-skew trim increment DKEN = 1 350 ps
(1) RT is the single-ended termination resistance at the receiver end of the DVI link
(2) Black and white checkerboard pattern, each checker is one pixel wide.
(3) Assumes all inputs to the transmitter are not toggling.
(4) Rise and fall times are measured as the time between 20% and 80% of signal amplitude.
(5) Measured differentially at the 50% crossing point using the IDCK+ input clock as a trigger.
(6) Relative to input clock (IDCK).

6.6 Timing Requirements

MIN NOM MAX UNIT
t(pixel) Pixel time period(1) 6.06 40 ns
t(IDCK) IDCK duty cycle 30% 70%
t(ijit) IDCK clock jitter tolerance 2 ns
tsk(CC) DVI output inter-pair or channel-to-channel skew (2), see Figure 2 f(IDCK) = 165 MHz 1.2 ns
tsu(IDF) Data, DE, VSYNC, HSYNC setup time to IDCK+ falling edge, see Figure 2 Single edge (BSEL=1, DSEL=0,
DKEN=0, EDGE=0)
1.2 ns
th(IDF) Data, DE, VSYNC, HSYNC hold time to IDCK+ falling edge, see Figure 2 1.3 ns
tsu(IDR) Data, DE, VSYNC, HSYNC setup time to IDCK+ rising edge, see Figure 2 Single edge (BSEL=1, DSEL=0,
DKEN=0, EDGE=1)
1.2 ns
th(IDR) Data, DE, VSYNC, HSYNC hold time to IDCK+ rising edge, see Figure 2 1.3 ns
tsu(ID) Data, DE, VSYNC, HSYNC setup time to IDCK+ falling/rising edge, see Figure 3 Dual edge(BSEL=0,
DSEL=1, DKEN=0)
0.9 ns
th(ID) Data, DE, VSYNC, HSYNC hold time to IDCK+ falling/rising edge, see Figure 3 Dual edge (BSEL=0,
DSEL=1, DKEN=0)
1 ns
(1) t(pixel) is the pixel time defined as the period of the TXC output clock. The period of IDCK is equal to t(pixel).
(2) Measured differentially at the 50% crossing point using the IDCK+ input clock as a trigger.
td_dvi_out_slds145.gifFigure 1. Rise and Fall Time for DVI Outputs
td_ctrl_sngl_idck_slds145.gifFigure 2. Control and Single-Edge-Data Setup/Hold Time to IDCK±
td_dual_edge_idck_slds145.gifFigure 3. Dual Edge Data Setup/Hold Times to IDCK+
td_analog_dffrntl_slds145.gifFigure 4. Analog Output Intra-Pair ± Differential Skew
td_analog_ch_to_ch_slds145.gifFigure 5. Analog Output Channel-to-Channel Skew

6.7 Typical Characteristics

typapp1_slds145.gifFigure 6. RTFDAJ vs Vswing