SLOS423H September   2003  – December 2015 THS3091 , THS3095

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics THS3091
    6. 6.6  Electrical Characteristics THS3095
    7. 6.7  Dissipation Ratings Table
    8. 6.8  Typical Characteristics
    9. 6.9  Typical Characteristics (±15 V)
    10. 6.10 Typical Characteristics (±5 V)
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 Saving Power With Power-Down Functionality and Setting Threshold Levels With the Reference Pin
      2. 7.2.2 Power-Down Reference Pin Operation
    3. 7.3 Device Functional Modes
      1. 7.3.1 Wideband, Noninverting Operation
      2. 7.3.2 Wideband, Inverting Operation
      3. 7.3.3 Single-Supply Operation
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video Distribution
      2. 8.1.2 Driving Capacitive Loads
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PowerPAD Design Considerations
      1. 10.3.1 PowerPAD Layout Considerations
      2. 10.3.2 Power Dissipation and Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Fixtures, Spice Models, and Application Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DDA|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Video Distribution

The wide bandwidth, high slew rate, and high output drive current of the THS309x matches the demands for video distribution for delivering video signals down multiple cables. To ensure high signal quality with minimal degradation of performance, a 0.1-dB gain flatness should be at least 7x the passband frequency to minimize group delay variations from the amplifier. A high slew rate minimizes distortion of the video signal, and supports component video and RGB video signals that require fast transition times and fast settling times for high signal quality.

THS3091 THS3095 ai_cap_load_los423.gif Figure 63. Video Distribution Amplifier Application

8.1.2 Driving Capacitive Loads

Applications such as FET line drivers can be highly capacitive and cause stability problems for high-speed amplifiers.

Figure 64 through Figure 69 show recommended methods for driving capacitive loads. The basic idea is to use a resistor or ferrite chip to isolate the phase shift at high frequency caused by the capacitive load from the amplifier’s feedback path. See SLOA013 for recommended resistor values versus capacitive load.

THS3091 THS3095 riso_v15_cl_los423.gif Figure 64. Recommended RISO vs Capacitive Load
THS3091 THS3095 ai_largeCL_los423.gif Figure 65. Driving a Large Capacitive Load Using an Output Series Isolation Resistor
THS3091 THS3095 ai_2CL_large_los423.gif Figure 66. Driving a Large Capacitive Load Using an Output Series Ferrite Bead

Placing a small series resistor, RISO, between the amplifier’s output and the capacitive load, as shown in Figure 65, is an easy way of isolating the load capacitance.

Using a ferrite chip in place of RISO, as shown in Figure 66, is another approach of isolating the output of the amplifier. The ferrite's impedance characteristic versus frequency is useful to maintain the low-frequency load independence of the amplifier while isolating the phase shift caused by the capacitance at high frequency. Use a ferrite with similar impedance to RISO, 20 Ω to 50 Ω, at 100 MHz and low-impedance at DC.

Figure 67 shows another method used to maintain the low-frequency load independence of the amplifier while isolating the phase shift caused by the capacitance at high frequency. At low frequency, feedback is mainly from the load side of RISO. At high frequency, the feedback is mainly via the 27-pF capacitor. The resistor RIN in series with the negative input is used to stabilize the amplifier and should be equal to the recommended value of RF at unity gain. Replacing RIN with a ferrite of similar impedance at about 100 MHz as shown in Figure 68 gives similar results with reduced DC offset and low-frequency noise. (See the Related Documentation section for expanding the usability of current-feedback amplifiers.)

THS3091 THS3095 ai_ampB_CL2_los423.gif Figure 67. Driving a Large Capacitive Load Using a Multiple Feedback Loop With Stabilizing Input Resistor (RIN)
THS3091 THS3095 ai_ampA_CL2_los423.gif Figure 68. Driving a Large Capacitive Load Using a Multiple Feedback Loop With Stabilizing Input Ferrite Bead (FIN)

Figure 69 is shown using two amplifiers in parallel to double the output drive current to larger capacitive loads. This technique is used when more output current is needed to charge and discharge the load faster like when driving large FET transistors.

THS3091 THS3095 ai_LBE_ee_los423.gif Figure 69. Driving a Large Capacitive Load Using 2 Parallel Amplifier Channels

Figure 70 shows a push-pull FET driver circuit typical of ultrasound applications with isolation resistors to isolate the gate capacitance from the amplifier.

THS3091 THS3095 ai_driveCL_los423.gif Figure 70. PowerFET Drive Circuit

8.2 Typical Application

The fundamental concept of load sharing is to drive a load using two or more of the same operational amplifiers. Each amplifier is driven by the same source. Figure 71 shows two THS3091 amplifiers sharing the same load. This concept effectively reduces the curernt load of each amplifier by 1/N, where N is the number of amplifiers.

THS3091 THS3095 ai_reference_ths3091_load_share_boa127.gif Figure 71. Reference THS3091 and THS3091 Load Sharing Test Configurations

8.2.1 Design Requirements

Use two THS3091 amplifiers in a parallel load-sharing circuit to improve distortion performance.

Table 5. Design Parameters

DESIGN PARAMETER VALUE
VOPP 20 V
RLOAD 100 Ω

8.2.2 Detailed Design Procedure

In addition to providing higher output current drive to the load, the load sharing configuration can also provide improved distortion performance. In many cases, an operational amplifier shows better distortion performance as the load current decreases (that is, for higher resistive loads) until the feedback resistor starts to dominate the current load. In a load sharing configuration of N amplifiers in parallel, the equivalent current load that each amplifier drives is 1/N times the total load current. For example, in a two-amplifier load sharing configuration with matching resistance (refer to Figure 71) driving a resistive load (RL), each series resistance is 2*RL and each amplifier drives 2*RL . A convenient indicator of whether an op amp will function well in a load sharing configuration is the characteristic performance graph of harmonic distortion versus load resistance. Such graphs can be found in most of TI’s high-speed amplifier data sheets. These graphs can be used to obtain a general sense of whether or not an amplifier will show improved distortion performance in load sharing configurations.

Two test circuits are shown in Figure 71, one for a single THS3091 amplifier driving a double-terminated, 50-Ω cable and one with two THS3091 amplifiers in a load sharing configuration. In the load sharing configuration, the two 100-Ω series output resistors act in parallel to provide 50-Ω back-matching to the 50-Ω cable.

Figure 72 and Figure 73 show the 32-MHz, 18-VPP sine wave output amplitudes for the single THS3091 configuration and the load sharing configuration, respectively, measured using an oscilloscope. An ideal sine wave is also included as a visual reference (the dashed red line). Figure 72 shows visible distortion in the single THS3091 output. In the load sharing configuration of Figure 73, however, no obvious degradation is visible.

Figure 74 and Figure 75 show the 64-MHz sine wave outputs of the two configurations from Figure 8. While the single THS3091 output is clearly distorted in Figure 74, the output of the load sharing configuration in Figure 75 shows only minor deviations from the ideal sine wave.

The improved output waveform as a result of load sharing is quantified in the harmonic distortion versus frequency graphs shown in Figure 76 and Figure 77 for the single amplifier and load sharing configurations, respectively. While second-harmonic distortion remains largely the same between the single and load sharing cases, third-harmonic distortion is improved by approximately 8 dB in the frequency range between 20 MHz to 64 MHz.

Table 6. Bill of Materials

THS3091DDA and THS3095DDA EVM(1)
ITEM DESCRIPTION SMD
SIZE
REFERENCE
DESIGNATOR
PCB
QTY
MANUFACTURER'S
PART NUMBER
DISTRIBUTOR'S
PART NUMBER
1 Bead, Ferrite, 3 A, 80 Ω 1206 FB1, FB2 2 (Steward) HI1206N800R-00 (Digi-Key) 240-1010-1-ND
2 Cap, 6.8 μF, Tantalum, 50 V, 10% D C3, C6 2 (AVX) TAJD685K050R (Garrett) TAJD685K050R
3 Cap, 0.1 μF, ceramic, X7R, 50 V 0805 C9, C10 2(2) (AVX) 08055C104KAT2A (Garrett) 08055C104KAT2A
4 Cap, 0.1 μF, ceramic, X7R, 50 V 0805 C4, C7 2 (AVX) 08055C104KAT2A (Garrett) 08055C104KAT2A
5 Resistor, 0 Ω, 1/8 W, 1% 0805 R9 1(2) (KOA) RK73Z2ALTD (Garrett) RK73Z2ALTD
6 Resistor, 249 Ω, 1/8 W, 1% 0805 R3 1 (KOA) RK73H2ALTD2490F (Garrett) RK73H2ALTD2490F
7 Resistor, 1 kΩ, 1/8 W, 1% 0805 R4 1 (KOA) RK73H2ALTD1001F (Garrett) RK73H2ALTD1001F
8 Open 1206 R8 1
9 Resistor, 0 Ω, 1/4 W, 1% 1206 R1 1 (KOA) RK73Z2BLTD (Garrett) RK73Z2BLTD
10 Resistor, 49.9 Ω, 1/4 W, 1% 1206 R2, R7 2 (KOA) RK73Z2BLTD49R9F (Garrett) RK73Z2BLTD49R9F
11 Open 2512 R5, R6 2
12 Header, 0.1-inch (2,54 mm) centers,
0.025-inch (6,35 mm) square pins
JP1, JP2 2 (2) (Sullins) PZC36SAAN (Digi-Key) S1011-36-ND
13 Connector, SMA PCB Jack J1, J2, J3 3 (Amphenol) 901-144-8RFX (Newark) 01F2208
14 Jack, banana receptacle,
0.25-inch (6,35 mm) dia. hole
J4, J5, J6 3 (SPC) 813 (Newark) 39N867
15 Test point, black TP1, TP2 2 (Keystone) 5001 (Digi-Key) 5001K-ND
16 Standoff, 4-40 hex,
0.625-inch (15,9 mm) length
4 (Keystone) 1808 (Newark) 89F1934
17 Screw, Phillips, 4-40,
0.25-inch (6,35 mm)
4 SHR-0440-016-SN
18 IC, THS3091(3)
IC, THS3095(2)
U1 1 (TI) THS3091DDA(3)
(TI) THS3095DDA(2)
19 Board, printed-circuit 1 (TI) EDGE # 6446289 Rev. A(3)
(TI) EDGE # 6446290 Rev. A(2)
(1) All items are designated for both the THS3091DDA and THS3095 EVMs unless otherwise noted.
(2) THS3095 EVM only.
(3) THS3091 EVM only.

8.2.3 Application Curves

THS3091 THS3095 tc_sgl_ths3091_32mhz_output_boa127.gif Figure 72. 32-MHz Sine Wave Output (Gain = 5 V/V, Signal Amplitude Referred to Amplifier Output), Single THS3091 Circuit Configuration
THS3091 THS3095 tc_sgl_ths3091_64mhz_output_boa127.gif Figure 74. 64-MHz Sine Wave Output (Gain = 5 V/V, Signal Amplitude Referred to Amplifier Output), Single THS3091 Circuit Configuration
THS3091 THS3095 tc_harm_dist_fqcy_sgl_ths3091_boa127.gif Figure 76. Harmonic Distortion vs Frequency, Single THS3091 Circuit Configuration
THS3091 THS3095 tc_dbl_ths3091_32mhz_output_boa127.gif Figure 73. 32-MHz Sine Wave Output (Gain = 5 V/V, Signal Amplitude Referred to Amplifier Output), Two THS3091 Amplifiers in Load Sharing Configuration
THS3091 THS3095 tc_dbl_ths3091_64mhz_output_boa127.gif Figure 75. 64-MHz Sine Wave Output (Gain = 5 V/V, Signal Amplitude Referred to Amplifier Output), Two THS3091 Amplifiers in Load Sharing Configuration
THS3091 THS3095 tc_harm_dist_fqcy_dbl_ths3091_boa127.gif Figure 77. Harmonic Distortion vs Frequency, Two THS3091 Amplifiers in Load Sharing Configuration