SLOS423H September   2003  – December 2015 THS3091 , THS3095

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics THS3091
    6. 6.6  Electrical Characteristics THS3095
    7. 6.7  Dissipation Ratings Table
    8. 6.8  Typical Characteristics
    9. 6.9  Typical Characteristics (±15 V)
    10. 6.10 Typical Characteristics (±5 V)
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Feature Description
      1. 7.2.1 Saving Power With Power-Down Functionality and Setting Threshold Levels With the Reference Pin
      2. 7.2.2 Power-Down Reference Pin Operation
    3. 7.3 Device Functional Modes
      1. 7.3.1 Wideband, Noninverting Operation
      2. 7.3.2 Wideband, Inverting Operation
      3. 7.3.3 Single-Supply Operation
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Video Distribution
      2. 8.1.2 Driving Capacitive Loads
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 PowerPAD Design Considerations
      1. 10.3.1 PowerPAD Layout Considerations
      2. 10.3.2 Power Dissipation and Thermal Considerations
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Fixtures, Spice Models, and Application Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DDA|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

Achieving optimum performance with a high-frequency amplifier, like the THS309x, requires careful attention to board layout parasitic and external component types.

Recommendations that optimize performance include:

  • Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and input pins can cause instability. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board.
  • Minimize the distance [< 0.25 inch (6.35 mm)] from the power supply pins to high-frequency 0.1-μF and 100-pF decoupling capacitors. At the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power supply connections should always be decoupled with these capacitors. Larger (6.8 μF or more) tantalum decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board.
  • Careful selection and placement of external components preserve the high-frequency performance of the THS309x. Resistors should be a low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Again, keep their leads and PC board trace length as short as possible. Never use wire-bound type resistors in a high-frequency application. Because the output pin and inverting input pins are the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as possible to the inverting input pins and output pins. Other network components, such as input termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values > 2 kΩ, this parasitic capacitance can add a pole and/or a zero that can effect circuit operation. Keep resistor values as low as possible, consistent with load-driving considerations.
  • Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces [0.05 inch (1.3 mm) to 0.1 inch (2.54 mm)] should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (< 4 pF) may not need an RS because the THS309x are nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is not necessary onboard, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS309x is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device; this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly terminated transmission line is unacceptable, a long trace can be series- terminated at the source end only. Treat the trace as a capacitive load in this case. This does not preserve signal integrity as well as a doubly terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance.
  • Socketing a high-speed part like the THS309x is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS309x parts directly onto the board.

10.2 Layout Example

THS3091 THS3095 layout_ex_slos423.png Figure 78. Layout Recommendation
THS3091 THS3095 evm_circuit_los423.gif Figure 79. THS3091 EVM Circuit Configuration
THS3091 THS3095 ai_evm_top_los423.gif Figure 80. THS3091 EVM Board Layout (Top Layer)
THS3091 THS3095 ai_evm_mid_los423.gif Figure 81. THS3091 EVM Board Layout (Second and Third Layers)
THS3091 THS3095 ai_evm_bot_los423.gif Figure 82. THS3091 EVM Board Layout (Bottom Layer)

10.3 PowerPAD Design Considerations

The THS309x are available in a thermally-enhanced PowerPAD family of packages. These packages are constructed using a downset leadframe on which the die is mounted [see Figure 83(a) and Figure 83(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see Figure 83(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad. Note that devices such as the THS309x have no electrical connection between the PowerPAD and the die.

The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat-dissipating device.

The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface mount with the, heretofore, awkward mechanical methods of heatsinking.

THS3091 THS3095 ai_thermal_los423.gif Figure 83. Views of Thermal Enhanced Package

Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach.

THS3091 THS3095 ai_etch_via_los423.gif Figure 84. DDA PowerPAD PCB Etch and via Pattern

10.3.1 PowerPAD Layout Considerations

  1. PCB with a top-side etch pattern is shown in Figure 84. There should be etch for the leads as well as etch for the thermal pad.
  2. Place 13 holes in the area of the thermal pad. These holes should be 0.01 inch (0.254 mm) in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.
  3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS309x IC. These additional vias may be larger than the 0.01-inch (0.254 mm) diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem.
  4. Connect all holes to the internal ground plane. Note that the PowerPAD is electrically isolated from the silicon and all leads. Connecting the PowerPAD to any potential voltage such as VS– is acceptable as there is no electrical connection to the silicon.
  5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the holes under the THS309x PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole.
  6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its 13 holes exposed. The bottom-side solder mask should cover the 13 holes of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the reflow process.
  7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
  8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed.

10.3.2 Power Dissipation and Thermal Considerations

The THS309x incorporates automatic thermal shutoff protection. This protection circuitry shuts down the amplifier if the junction temperature exceeds approximately 160°C. When the junction temperature reduces to approximately 140°C, the amplifier turns on again. But, for maximum performance and reliability, the designer must ensure that the design does not exceed a junction temperature of 125°C. Between 125°C and 150°C, damage does not occur, but the performance of the amplifier begins to degrade and long-term reliability suffers. The thermal characteristics of the device are dictated by the package and the PC board. Maximum power dissipation for a given package can be calculated using the following formula.

Equation 4. THS3091 THS3095 Q_PDmax_lvs423.gif

For systems where heat dissipation is more critical, the THS3091 and THS3095 are offered in an 8-pin SOIC (DDA) with PowerPAD package. The thermal coefficient for the PowerPAD packages are substantially improved over the traditional SOIC. Maximum power dissipation levels are depicted in the graph for the available packages. The data for the PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application note (SLMA002). If the PowerPAD is not soldered to the PCB, the thermal impedance will increase substantially which may cause serious heat and performance issues. Be sure to always solder the PowerPAD to the PCB for optimum performance.

When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to consider not only quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem.

THS3091 THS3095 line.gif