SBOS778D April   2016  – April 2021 THS4551


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Companion Devices
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: (VS+) – (VS–) = 5 V
    6. 7.6 Electrical Characteristics: (VS+) – (VS–) = 3 V
    7. 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 7.9 Typical Characteristics: 3-V to 5-V Supply Range
  8. Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 8.3 Output Common-Mode Measurements
    4. 8.4 Differential Amplifier Noise Measurements
    5. 8.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 8.6 Simulated Characterization Curves
    7. 8.7 Terminology and Application Assumptions
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential Open-Loop Gain and Output Impedance
      2. 9.3.2 Setting Resistor Values Versus Gain
      3. 9.3.3 I/O Headroom Considerations
      4. 9.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      2. 9.4.2 Operation from a Differential Input to a Differential Output
        1. AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. DC-Coupled, Differential-Input to Differential-Output Design Issues
      3. 9.4.3 Input Overdrive Performance
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Noise Analysis
      2. 10.1.2 Factors Influencing Harmonic Distortion
      3. 10.1.3 Driving Capacitive Loads
      4. 10.1.4 Interfacing to High-Performance Precision ADCs
      5. 10.1.5 Operating the Power Shutdown Feature
      6. 10.1.6 Designing Attenuators
      7. 10.1.7 The Effect of Adding a Feedback Capacitor
    2. 10.2 Typical Applications
      1. 10.2.1 An MFB Filter Driving an ADC Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 10.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 10.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Analysis
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Layout Recommendations
    2. 12.2 Layout Example
    3. 12.3 EVM Board
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 TINA-TI Simulation Model Features
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

TINA-TI Simulation Model Features

The device model is available on the product folder under in a typical application circuit file. The model includes numerous features intended to speed designer progress over a wide range of application requirements. The following list shows the performance parameters included in the model:

  • For the small-signal response shape with any external circuit:
    • Differential open-loop gain and phase
    • Parasitic input capacitance
    • Open-loop differential output impedance
  • For noise simulations:
    • Input differential spot voltage noise and a 100-Hz 1/f corner
    • Input current noise on each input with a 6-kHz 1/f corner
  • For time-domain, step-response simulations:
    • Differential slew rate
    • I/O headroom models to predict clipping
    • Input stage diodes to predict overdrive limiting
  • Fine-scale, dc precision terms:
    • PSRR
    • CMRR

The Section 7.9 provides more detail than the macromodels can provide; some of the unmodeled features include:

  • Harmonic distortion
  • Temperature drift in dc error terms (VIO and IOS)
  • Overdrive recovery time
  • Turn-on and turn-off times using the power-down feature

Some unique simulation considerations come with the THS4551 TINA-TI™ model. This device (and model) include 0.6-pF internal feedback capacitors. These capacitors are intended to improve phase margin when using higher external feedback resistor values. Higher feedback resistors generate an in-band pole in the feedback signal with the differential input capacitance, and the internal 0.6 pF capacitors add a zero to the feedback response shape to shape the noise gain flat at the loop-gain crossover.

In order to generate an accurate open-loop gain and phase simulation, these components must be removed because they are feedback elements, not forward path elements. Figure 13-1 illustrates a typical AOL gain and phase simulation (available as a TINA-TI™ software file) where external –0.6-pF capacitors cancel out the internal capacitors in the model (TINA-TI™ supports negative value elements). The inductors inside the loop close the loop for the dc operating point and open the loop immediately for an ac sweep. The input-coupling capacitors are open at dc, then couple in the differential input immediately on an ac sweep. The somewhat odd values help reduce numerical chatter in the simulation. When using the internal feedback traces from the outputs to the inputs on the RGT package, be sure to add the 3.3-Ω trace impedance to any simulation. This impedance is not included in the core model.

GUID-6EBC1A47-74A6-4D32-AEDF-75525BFA3087-low.gifFigure 13-1 Open-Loop Gain and Phase TINA-TI™ Simulation Setup

This test is set up with a very light load to isolate the no load AOL curve. Adding a load brings in the open-loop ZOL response to the overall response of the output pins. Running this simulation gives the gain and phase of Figure 13-2 that closely matches the plot of Figure 7-37.

GUID-CF887173-9DE0-4D56-96B8-CADABA84927D-low.gifFigure 13-2 Open-Loop Gain and Phase Simulation Result