The design proceeds as follows:
- Select the feedback resistor to be 1 kΩ and use the values from Table 9-1 at a gain of 5 V/V to implement a
50-Ω input match with a gain of 5 V/V.
- Use a 3.3-V power supply and apply the ADC output common-mode voltage to the VOCM input pin of the THS4551.
- Design a –1-dB insertion loss, 2nd-order RLC filter using the approach described in the RLC Filter Design for ADC Interface Applications application note (SBAA108).
- Adjust the total resistive load target in the filter design to hit the standard value for the filter inductors.
- Convert the filter design to differential with only differential shunt elements. These elements must not be split and connected to a center-point ground. This technique passes the output common-mode voltage from the FDA to the ADC with no level shift error.
- Add a small series resistor at the ADC inputs. This resistor is not part of the filter design but spreads out the sampling glitch energy to provide improved SFDR.
- Check the common-mode level shift from the FDA outputs to the ADC resulting from the clock-rate-dependent common-mode current. This common-mode current into the ADC shifts the common-mode voltage slightly, but can easily stay in range with a low series resistor in the filter design.