SBOS778D April   2016  – April 2021 THS4551


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Companion Devices
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: (VS+) – (VS–) = 5 V
    6. 7.6 Electrical Characteristics: (VS+) – (VS–) = 3 V
    7. 7.7 Typical Characteristics: (VS+) – (VS–) = 5 V
    8. 7.8 Typical Characteristics: (VS+) – (VS–) = 3 V
    9. 7.9 Typical Characteristics: 3-V to 5-V Supply Range
  8. Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Output Interface Circuit for DC-Coupled Differential Testing
    3. 8.3 Output Common-Mode Measurements
    4. 8.4 Differential Amplifier Noise Measurements
    5. 8.5 Balanced Split-Supply Versus Single-Supply Characterization
    6. 8.6 Simulated Characterization Curves
    7. 8.7 Terminology and Application Assumptions
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential Open-Loop Gain and Output Impedance
      2. 9.3.2 Setting Resistor Values Versus Gain
      3. 9.3.3 I/O Headroom Considerations
      4. 9.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversions
        2. DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
      2. 9.4.2 Operation from a Differential Input to a Differential Output
        1. AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. DC-Coupled, Differential-Input to Differential-Output Design Issues
      3. 9.4.3 Input Overdrive Performance
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Noise Analysis
      2. 10.1.2 Factors Influencing Harmonic Distortion
      3. 10.1.3 Driving Capacitive Loads
      4. 10.1.4 Interfacing to High-Performance Precision ADCs
      5. 10.1.5 Operating the Power Shutdown Feature
      6. 10.1.6 Designing Attenuators
      7. 10.1.7 The Effect of Adding a Feedback Capacitor
    2. 10.2 Typical Applications
      1. 10.2.1 An MFB Filter Driving an ADC Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 10.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 10.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Thermal Analysis
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Board Layout Recommendations
    2. 12.2 Layout Example
    3. 12.3 EVM Board
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 TINA-TI Simulation Model Features
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Example Characterization Circuits

The THS4551 offers the advantages of a fully differential amplifier (FDA) design with the trimmed input offset voltage and very low drift of a precision op amp. The FDA is an extremely flexible device where the main aim is to provide a purely differential output signal centered on a user-configurable common-mode voltage usually matched to the input common-mode voltage required by an analog-to-digital converter (ADC) following this stage. The primary options revolve around the choices of single-ended or differential inputs, ac-coupled or dc-coupled signal paths, gain targets, and resistor value selections. The characterizations described in this section focus on single-ended input to differential output designs as the more challenging application requirement. Differential sources can certainly be supported and are often simpler to both implement and analyze.

The characterization circuits are typically operated with a single-ended, matched, 50-Ω, input termination to a differential output at the FDA output pins because most lab equipment is single-ended. The FDA differential output is then translated back to single-ended through a variety of baluns (or transformers), depending on the test and frequency range. DC-coupled step response testing used two 50-Ω scope inputs with trace math. Single-supply operation is most common in end equipment designs. However, using split balanced supplies allows simple ground referenced testing without adding further blocking capacitors in the signal path beyond those capacitors already within the test equipment. The starting point for any single-ended input to differential output measurements (such as any of the frequency response curves) is shown in Figure 8-1 (available as a TINA-TI™ simulation file).

GUID-042F95A1-83E9-47DD-B28F-61ACE8D33829-low.gifFigure 8-1 Single-Ended Source to a Differential Gain of a 1-V/V Test Circuit

Most characterization plots fix the RF (RF1 = RF2) value at 1 kΩ, as shown in Figure 8-1. This element value is completely flexible in application, but 1 kΩ provides a good compromise for the parasitic issues linked to this value, specifically:

  • Added output loading: the FDA functions similarly to an inverting op amp design with both feedback resistors appearing as an added load across the outputs (the approximate total differential load in Figure 8-1 is 1 kΩ || 2 kΩ = 667 Ω). The 1-kΩ value also reduces the power dissipated in the feedback networks.
  • Noise contributions resulting from resistor values: these contributions are both the 4kTRF terms and the current noise times the RF value to the output (see Section 10.1.1).
  • Parasitic feedback pole at the input summing nodes: this pole is created by the feedback resistor (RF) value and the 1.2-pF differential input capacitance (as well as any board layout parasitic) and introduces a zero in the noise gain, thus decreasing the phase margin in most situations. This effect must be managed for best frequency response flatness or step response overshoot. Internal 0.6-pF feedback capacitors on each side combine with these external feedback resistors to introduce a zero in the noise gain, thereby reducing the effect of the feedback pole to the differential input capacitance.

The frequency domain characterization curves start with the selections of Figure 8-1. Some of the features in this test circuit include:

  • The elements on the non-signal input side exactly match the signal input resistors. This feature has the effect of more closely matching the divider networks on each side of the FDA. The three resistors on the non-signal input side can be replaced by a single resistor to ground using a standard E96 value of 1.02 kΩ with some loss in gain balancing between the two sides; see Section 9.3.4).
  • Translating from a 1-kΩ differential load to a 50-Ω environment introduces considerable insertion loss in the measurements (–31.8 dB in Figure 8-1). The measurement path insertion loss is normalized out when reporting the frequency response curves to show the gain response to the FDA output pins.
  • In the pass band for the output balun, the network analyzer 50-Ω load reflects to be in parallel with the 52.3-Ω shunt termination. These elements combine to show a differential 1-kΩ load at the output pins of the THS4551. The source impedance presented to the balun is a differential 50-Ω source. Figure 8-2 and Figure 8-3 show the TINA-TI™ model (available as a TINA-TI™ simulation file) and resulting response flatness for this relatively low-frequency balun providing 0.1-dB flatness through 100 MHz.
GUID-377EB500-1120-4780-9572-7931EB82AB83-low.gifFigure 8-2 Output Measurement Balun Simulation Circuit in TINA-TI™
GUID-29F61D9C-D5A9-4075-ADE5-EEA383684BCB-low.gifFigure 8-3 Output Measurement Balun Flatness Test

Starting from the test circuit of Figure 8-1, various elements are modified to show the effect of these elements over a range of design targets, specifically:

  • The gain setting is changed by adjusting the RT and the two RG elements to provide a 50-Ω input match and setting the feedback resistors to 1 kΩ.
  • Output loading of both resistive and capacitive load testing. Changing to lower resistive loads is accomplished by adding parallel resistors across the output pins in Figure 8-1. Changing to capacitive loads adds series output resistors to a differential capacitance before the 1-kΩ sense path of Figure 8-1.
  • Power-supply settings. Most often, a single 5-V test uses a ±2.5-V supply and a 3-V test uses ±1.5-V supplies with the VOCM input control at ground.
  • The disable control pin ( PD) is tied to the positive supply (VS+) for any active channel test.