SLLSF78B December   2020  – October 2021 THVD1400 , THVD1420

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  ESD Ratings [IEC]
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Power Dissipation Characteristics
    7. 5.7  Electrical Characteristics
    8. 5.8  Switching Characteristics (THVD1400)
    9. 5.9  Switching Characteristics (THVD1420)
    10. 5.10 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Data Rate and Bus Length
        2. 8.2.1.2 Stub Length
        3. 8.2.1.3 Bus Loading
        4. 8.2.1.4 Receiver Failsafe
        5. 8.2.1.5 Transient Protection
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Driver
│VOD│ Driver differential-output voltage magnitude RL = 60 Ω, -7 V ≤ Vtest ≤ 12 V See Figure 6-1  1.5 2 V
RL = 60 Ω, -7 V ≤ Vtest ≤ 12 V, 4.5 V ≤ Vcc ≤ 5.5 V 2.1 3
RL = 100 Ω, CL = 50 pF See Figure 6-2  2 2.5
RL = 54 Ω, CL = 50 pF 1.5 2
RL = 54 Ω, 4.5 V ≤ Vcc ≤ 5.5 V 2.1 3
Δ│VOD│ Change in magnitude of driver differential-output voltage RL = 54 Ω or 100 Ω, CL = 50 pF See Figure 6-2  –50 50 mV
VOC(SS) Steady-state common-mode output voltage 1 VCC / 2 3 V
ΔVOC Change in differential driver common-mode output voltage –50 50 mV
VOC(PP) Peak-to-peak driver common-mode output voltage RL = 54 Ω,  CL = 50 pF, VCC = 5 V See Figure 6-2  520 mV
VOC(PP) Peak-to-peak driver common-mode output voltage RL = 54 Ω, CL = 50 pF, VCC = 3.3 V  See Figure 6-2  250 mV
│IOS│ Driver short-circuit output current DE = VCC, -7 V ≤ [VA or VB] ≤ 12 V, or A pin shorted to B pin -250 250 mA
Receiver
II Bus input current (driver disabled) DE = 0 V, VCC = 0 V or 5.5 V VI = 12 V 75 100 µA
VI = –7 V –97 –70
VIT+ Positive-going receiver differential-input voltage threshold -7 V ≤ VCM ≤ 12 V –70 –45 mV
VIT– Negative-going receiver differential-input voltage threshold –200 –150 mV
VHYS(1) Receiver differential-input voltage threshold hysteresis (VIT+ – VIT– ) 30 50 mV
VOH Receiver high-level output voltage IOH = –4 mA VCC – 0.4 VCC – 0.2 V
VOL Receiver low-level output voltage IOL = 4 mA 0.2 0.4 V
IOZ Receiver high-impedance output current VO = 0 V or VCC, RE = VCC –1 1 µA
Logic
IIN Input current (D, DE, RE) –5 5 µA
Supply
ICC Supply current (quiescent) VCC = 3.6 V Both driver and receiver enabled DE = VCC, RE = 0, no load 1500 1800 µA
Driver enabled and receiver disabled DE = VCC, RE = VCC, no load 1000 1500
Driver disabled and receiver enabled DE = 0, RE = 0, no load 700 900
Both driver and receiver disabled DE = 0 , RE = VCC, no load 0.1 1
VCC = 5.5 V Driver and receiver enabled DE = VCC, RE = 0, no load 1700 3000 µA
Driver enabled, receiver disabled DE = VCC, RE = VCC, no load 1300 2500
Driver disabled, receiver enabled DE = 0, RE = 0, no load 800 1000
Both driver and receiver disabled DE = 0, RE = VCC, no load 0.1 1
(1) Under any specific conditions, VIT+ is specified to be at least VHYS higher than VIT–.