SCPS260B
August 2017 – February 2020
TIC12400-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
Simplified Schematic
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
6.7
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
VS Pin
8.3.2
VDD Pin
8.3.3
Device Initialization
8.3.4
Device Trigger
8.3.5
Device Reset
8.3.5.1
VS Supply POR
8.3.5.2
Hardware Reset
8.3.5.3
Software Reset
8.3.6
VS Under-Voltage (UV) Condition
8.3.7
VS Over-Voltage (OV) Condition
8.3.8
Switch Inputs Settings
8.3.8.1
Input Current Source and Sink Selection
8.3.8.2
Input Mode Selection
8.3.8.3
Input Enable Selection
8.3.8.4
Thresholds Adjustment
8.3.8.5
Wetting Current Configuration
8.3.9
Interrupt Generation and INT Assertion
8.3.9.1
INT Pin Assertion Scheme
8.3.9.2
Interrupt Idle Time (tINT_IDLE) Time
8.3.9.3
Microcontroller Wake-Up
8.3.9.4
Interrupt Enable or Disable and Interrupt Generation Conditions
8.3.9.5
Detection Filter
8.3.10
Temperature Monitor
8.3.10.1
Temperature Warning (TW)
8.3.10.2
Temperature Shutdown (TSD)
8.3.11
Parity Check and Parity Generation
8.3.12
Cyclic Redundancy Check (CRC)
8.4
Device Functional Modes
8.4.1
Continuous Mode
8.4.2
Polling Mode
8.4.2.1
Standard Polling
8.4.2.2
Matrix polling
8.4.3
Additional Features
8.4.3.1
Clean Current Polling (CCP)
8.4.3.2
Wetting Current Auto-Scaling
8.4.3.3
VS Measurement
8.4.3.4
Wetting Current Diagnostic
8.4.3.5
ADC Self-Diagnostic
8.5
Programming
8.5.1
SPI Communication Interface Buses
8.5.1.1
Chip Select (CS)
8.5.1.2
System Clock (SCLK)
8.5.1.3
Slave In (SI)
8.5.1.4
Slave Out (SO)
8.5.2
SPI Sequence
8.5.2.1
Read Operation
8.5.2.2
Write Operation
8.5.2.3
Status Flag
8.6
REGISTER_MAPS
8.6.1
DEVICE_ID Register (Offset = 1h) [Reset = 20h]
Table 12.
DEVICE_ID Register Field Descriptions
8.6.2
INT_STAT Register (Offset = 2h) [reset = 1h]
Table 13.
INT_STAT Register Field Descriptions
8.6.3
CRC Register (Offset = 3h) [Reset = FFFFh]
Table 14.
CRC Register Field Descriptions
8.6.4
IN_STAT_MISC Register (Offset = 4h) [Reset = 0h]
Table 15.
IN_STAT_MISC Register Field Descriptions
8.6.5
IN_STAT_COMP Register (Offset = 5h) [Reset = 0h]
Table 16.
IN_STAT_COMP Register Field Descriptions
8.6.6
IN_STAT_ADC0 Register (Offset = 6h) [Reset = 0h]
Table 17.
IN_STAT_ADC0 Register Field Descriptions
8.6.7
IN_STAT_ADC1 Register (Offset = 7h) [Reset = 0h]
Table 18.
IN_STAT_ADC1 Register Field Descriptions
8.6.8
IN_STAT_MATRIX0 Register (Offset = 8h) [Reset = 0h]
Table 19.
IN_STAT_MATRIX0 Register Field Descriptions
8.6.9
IN_STAT_MATRIX1 Register (Offset = 9h) [Reset = 0h]
Table 20.
IN_STAT_MATRIX1 Register Field Descriptions
8.6.10
ANA_STAT0 Register (Offset = Ah) [Reset = 0h]
Table 21.
ANA_STAT0 Register Field Descriptions
8.6.11
ANA_STAT1 Register (Offset = Bh) [Reset = 0h]
Table 22.
ANA_STAT1 Register Field Descriptions
8.6.12
ANA_STAT2 Register (Offset = Ch) [Reset = 0h]
Table 23.
ANA_STAT2 Register Field Descriptions
8.6.13
ANA_STAT3 Register (Offset = Dh) [Reset = 0h]
Table 24.
ANA_STAT3 Register Field Descriptions
8.6.14
ANA_STAT4 Register (Offset = Eh) [Reset = 0h]
Table 25.
ANA_STAT4 Register Field Descriptions
8.6.15
ANA_STAT5 Register (Offset = Fh) [Reset = 0h]
Table 26.
ANA_STAT5 Register Field Descriptions
8.6.16
ANA_STAT6 Register (Offset = 10h) [reset = 0h]
Table 27.
ANA_STAT6 Register Field Descriptions
8.6.17
ANA_STAT7 Register (Offset = 11h) [Reset = 0h]
Table 28.
ANA_STAT7 Register Field Descriptions
8.6.18
ANA_STAT8 Register (Offset = 12h) [Reset = 0h]
Table 29.
ANA_STAT8 Register Field Descriptions
8.6.19
ANA_STAT9 Register (Offset = 13h) [Reset = 0h]
Table 30.
ANA_STAT9 Register Field Descriptions
8.6.20
ANA_STAT10 Register (Offset = 14h) [Reset = 0h]
Table 31.
ANA_STAT10 Register Field Descriptions
8.6.21
ANA_STAT11 Register (Offset = 15h) [Reset = 0h]
Table 32.
ANA_STAT11 Register Field Descriptions
8.6.22
ANA_STAT12 Register (Offset = 16h) [Reset = 0h]
Table 33.
ANA_STAT12 Register Field Descriptions
8.6.23
CONFIG Register (Offset = 1Ah) [Reset = 0h]
Table 34.
CONFIG Register Field Descriptions
8.6.24
IN_EN Register (Offset = 1Bh) [Reset = 0h]
Table 35.
IN_EN Register Field Descriptions
8.6.25
CS_SELECT Register (Offset = 1Ch) [Reset = 0h]
Table 36.
CS_SELECT Register Field Descriptions
8.6.26
WC_CFG0 Register (Offset = 1Dh) [Reset = 0h]
Table 37.
WC_CFG0 Register Field Descriptions
8.6.27
WC_CFG1 Register (Offset = 1Eh) [Reset = 0h]
Table 38.
WC_CFG1 Register Field Descriptions
8.6.28
CCP_CFG0 Register (Offset = 1Fh) [Reset = 0h]
Table 39.
CCP_CFG0 Register Field Descriptions
8.6.29
CCP_CFG1 Register (Offset = 20h) [Reset = 0h]
Table 40.
CCP_CFG1 Register Field Descriptions
8.6.30
THRES_COMP Register (Offset = 21h) [Reset = 0h]
Table 41.
THRES_COMP Register Field Descriptions
8.6.31
INT_EN_COMP1 Register (Offset = 22h) [Reset = 0h]
Table 42.
INT_EN_COMP1 Register Field Descriptions
8.6.32
INT_EN_COMP2 Register (Offset = 23h) [Reset = 0h]
Table 43.
INT_EN_COMP2 Register Field Descriptions
8.6.33
INT_EN_CFG0 Register (Offset = 24h) [Reset = 0h]
Table 44.
INT_EN_CFG0 Register Field Descriptions
8.6.34
INT_EN_CFG1 Register (Offset = 25h) [Reset = 0h]
Table 45.
INT_EN_CFG1 Register Field Descriptions
8.6.35
INT_EN_CFG2 Register (Offset = 26h) [Reset = 0h]
Table 46.
INT_EN_CFG2 Register Field Descriptions
8.6.36
INT_EN_CFG3 Register (Offset = 27h) [Reset = 0h]
Table 47.
INT_EN_CFG3 Register Field Descriptions
8.6.37
INT_EN_CFG4 Register (Offset = 28h) [Reset = 0h]
Table 48.
INT_EN_CFG4 Register Field Descriptions
8.6.38
THRES_CFG0 Register (Offset = 29h) [Reset = 0h]
Table 49.
THRES_CFG0 Register Field Descriptions
8.6.39
THRES_CFG1 Register (Offset = 2Ah) [Reset = 0h]
Table 50.
THRES_CFG1 Register Field Descriptions
8.6.40
THRES_CFG2 Register (Offset = 2Bh) [Reset = 0h]
Table 51.
THRES_CFG2 Register Field Descriptions
8.6.41
THRES_CFG3 Register (Offset = 2Ch) [Reset = X]
Table 52.
THRES_CFG3 Register Field Descriptions
8.6.42
THRES_CFG4 Register (Offset = 2Dh) [Reset = X]
Table 53.
THRES_CFG4 Register Field Descriptions
8.6.43
THRESMAP_CFG0 Register (Offset = 2Eh) [Reset = 0h]
Table 54.
THRESMAP_CFG0 Register Field Descriptions
8.6.44
THRESMAP_CFG1 Register (Offset = 2Fh) [Reset = 0h]
Table 55.
THRESMAP_CFG1 Register Field Descriptions
8.6.45
THRESMAP_CFG2 Register (Offset = 30h) [Reset = 0h]
Table 56.
THRESMAP_CFG2 Register Field Descriptions
8.6.46
Matrix Register (Offset = 31h) [Reset = 0h]
Table 57.
Matrix Register Field Descriptions
8.6.47
Mode Register (Offset = 32h) [Reset = 0h]
Table 58.
Mode Register Field Descriptions
8.7
Programming Guidelines
9
Application and Implementation
9.1
Application Information
9.2
Using TIC12400-Q1 in a 12 V Automotive System
9.3
Resistor-coded Switches Detection in Automotive Body Control Module
9.3.1
Design Requirements
9.3.2
Detailed Design Procedure
9.3.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Receiving Notification of Documentation Updates
12.2
Community Resources
12.3
Trademarks
12.4
Electrostatic Discharge Caution
12.5
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
DCP|38
MPDS520B
Thermal pad, mechanical data (Package|Pins)
DCP|38
PPTD170A
Orderable Information
scps260b_oa
scps260b_pm
1
Features
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature
Device HBM ESD Classification Level H2
Device CDM ESD Classification Level C4B
Designed to Support 12-V Automotive Systems with Over-voltage and Under-voltage Warning
Monitors up to 24 Direct Switch Inputs with 10 Inputs Configurable to Monitor Switches Connected to Either Ground or Battery
Switch Input Withstands up to 40 V (Load Dump Condition) and down to –24 V (Reverse Polarity Condition)
6 Configurable Wetting Current Settings:
(0 mA, 1 mA, 2 mA, 5 mA, 10 mA, and 15 mA)
Integrated 10-bit ADC for Multi-Position Analog Switch Monitoring
Integrated Comparator with 4 Programmable Thresholds for Digital Switch Monitoring
Ultra-low Operating Current in Polling Mode:
68 μA Typical (t
POLL
= 64 ms, t
POLL_ACT
= 128 μs,
All 24 Inputs Active, Comparator Mode, All Switches Open)
Interfaces Directly to MCU Using 3.3 V / 5 V Serial Peripheral Interface (SPI) Protocol
Interrupt Generation to Support Wake-Up Operation on All Inputs
Integrated Battery and Temperature Sensing
±8 kV Contact Discharge ESD Protection on Input Pins per ISO-10605 With Appropriate External Components
38-Pin TSSOP Package