SLLS177I March   1994  – March 2021 TL16C550C

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Recommended Operating Conditions (Low Voltage - 3.3 nominal)
    3. 5.3  Recommended Operating Conditions (Standard Voltage - 5 V nominal)
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics (Low Voltage - 3.3 V nominal)
    6. 5.6  Electrical Characteristics (Standard Voltage - 5 V nominal)
    7. 5.7  System Timing Requirements
    8. 5.8  System Switching Characteristics
    9. 5.9  Baud Generator Switching Characteristics
    10. 5.10 Receiver Switching Characteristics
    11. 5.11 Transmitter Switching Characteristics
    12. 5.12 Modem Control Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Autoflow Control (see Figure 1-1)
    2. 7.2 Auto-RTS (see Figure 1-1)
    3. 7.3 Auto-CTS (see Figure 1-1)
    4. 7.4 Enabling Autoflow Control and Auto-CTS
    5. 7.5 Auto-CTS and Auto-RTS Functional Timing
    6. 7.6 Functional Block Diagram
    7. 7.7 Principles of Operation
      1. 7.7.1  Accessible Registers
      2. 7.7.2  FIFO Control Register (FCR)
      3. 7.7.3  FIFO Interrupt Mode Operation
      4. 7.7.4  FIFO Polled Mode Operation
      5. 7.7.5  Interrupt Enable Register (IER)
      6. 7.7.6  Interrupt Identification Register (IIR)
      7. 7.7.7  Line Control Register (LCR)
      8. 7.7.8  Line Status Register (LSR)
      9. 7.7.9  Modem Control Register (MCR)
      10. 7.7.10 Modem Status Register (MSR)
      11. 7.7.11 Programming Baud Generator
      12. 7.7.12 Receiver Buffet Register (RBR)
      13. 7.7.13 Scratch Register
      14. 7.7.14 Transmitter Holding Register (THR)
  8. 8 Application Information
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.1 Accessible Registers

The system programmer, using the CPU, has access to and control over any of the ACE registers that are summarized in Table 7-2. These registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow Table 7-3.

Table 7-3 Summary of Accessible Registers
BIT NO. REGISTER ADDRESS
0 DLAB = 0 0 DLAB = 0 1 DLAB = 0 2 2 3 4 5 6 7 0 DLAB = 1 1 DLAB = 1
Receiver Buffer Register (Read Only) Transmitter Holding Register (Write Only) Interrupt Enable Register Interrupt Ident. Register (Read Only) FIFO Control Register (Write Only) Line Control Register Modem Control Register Line Status Register Modem Status Register Scratch Register Divisor Latch (LSB) Latch (MSB)
RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM
0 Data Bit 0(1) Data Bit 0 Enable Received Data Available Interrupt (ERBI) 0 if Interrupt Pending FIFO Enable Word Length Select Bit 0 (WLS0) Data Terminal Ready (DTR) Data Ready (DR) Delta Clear to Send (ΔCTS) Bit 0 Bit 0 Bit 8
1 Data Bit 1 Data Bit 1 Enable Transmitter Holding Register Empty Interrupt (ETBEI) Interrupt ID Bit 1 Receiver FIFO Reset Word Length Select Bit 1 (WLS1) Request to Send (RTS) Overrun Error (OE) Delta Data Set Ready (ΔDSR) Bit 1 Bit 1 Bit 9
2 Data Bit 2 Data Bit 2 Enable Receiver Line Status Interrupt (ELSI) Interrupt ID Bit 2 Transmitter FIFO Reset Number of Stop Bits (STB) OUT1 Parity Error (PE) Trailing Edge Ring Indicator (TERI) Bit 2 Bit 2 Bit 10
3 Data Bit 3 Data Bit 3 Enable Modem Status Interrupt (EDSSI) Interrupt ID Bit 3(2) DMA Mode Select Parity Enable (PEN) OUT2 Framing Error (FE) Delta Data Carrier Detect (ΔDCD) Bit 3 Bit 3 Bit 11
4 Data Bit 4 Data Bit 4 0 0 Reserved Even Parity Select (EPS) Loop Break Interrupt (BI) Clear to Send (CTS) Bit 4 Bit 4 Bit 12
5 Data Bit 5 Data Bit 5 0 0 Reserved Stick Parity Autoflow Control Enable (AFE) Transmitter Holding Register (THRE) Data Set Ready (DSR) Bit 5 Bit 5 Bit 13
6 Data Bit 6 Data Bit 6 0 FIFOs Enabled(2) Receiver Trigger (LSB) Break Control 0 Transmitter Empty (TEMT) Ring Indicator (RI) Bit 6 Bit 6 Bit 14
7 Data Bit 7 Data Bit 7 0 FIFOs Enabled(2) Receiver Trigger (MSB) Divisor Latch Access Bit (DLAB) 0 Error in RCVR FIFO(2) Data Carrier Detect (DCD) Bit 7 Bit 7 Bit 15
(1) Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
(2) These bits are always 0 in the TL16C450 mode.