The MSR is an 8-bit register that
provides information about the current state of the control lines from the modem,
data set, or peripheral device to the CPU. Additionally, four bits of this register
provide change information; when a control input from the modem changes state, the
appropriate bit is set. All four bits are cleared when the CPU reads the MSR. The
contents of this register are summarized in Table 7-3 and are described in the following bulleted list.
- Bit 0: This bit is the change in
clear-to-send (ΔCTS) indicator. ΔCTS indicates that the CTS
input has changed state since the last time it was read by the CPU. When ΔCTS is
set (autoflow control is not enabled and the modem status interrupt is enabled),
a modem status interrupt is generated. When autoflow control is enabled (ΔCTS is
cleared), no interrupt is generated.
- Bit 1: This bit is the change in
data set ready (ΔDSR) indicator. ΔDSR indicates that the
DSR input has changed state since the last time it was
read by the CPU. When ΔDSR isset and the modem status interrupt is enabled, a
modem status interrupt is generated.
- Bit 2: This bit is the trailing
edge of the ring indicator (TERI) detector. TERI indicates that the
RI input to the chip has changed from a low to a high
level. When TERI is set and the modem status interrupt is enabled, a modem
status interrupt is generated.
- Bit 3: This bit is the change in
data carrier detect (ΔDCD) indicator. ΔDCD indicates that the
DCD input to the chip has changed state since the last
time it was read by the CPU. When ΔDCD is set and the modem status interrupt is
enabled, a modem status interrupt is generated.
- Bit 4: This bit is the complement
of the clear-to-send (CTS) input. When the ACE is in the
diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1
(RTS).
- Bit 5: This bit is the complement
of the data set ready (DSR) input. When the ACE is in the
diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0
(DTR).
- Bit 6: This bit is the complement
of the ring indicator (RI) input. When the ACE is in the
diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 2
(OUT1).
- Bit 7: This bit is the complement
of the data carrier detect (DCD) input. When the ACE is in
the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3
(OUT2).