SLLS177I March   1994  – March 2021 TL16C550C

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Recommended Operating Conditions (Low Voltage - 3.3 nominal)
    3. 5.3  Recommended Operating Conditions (Standard Voltage - 5 V nominal)
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics (Low Voltage - 3.3 V nominal)
    6. 5.6  Electrical Characteristics (Standard Voltage - 5 V nominal)
    7. 5.7  System Timing Requirements
    8. 5.8  System Switching Characteristics
    9. 5.9  Baud Generator Switching Characteristics
    10. 5.10 Receiver Switching Characteristics
    11. 5.11 Transmitter Switching Characteristics
    12. 5.12 Modem Control Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Autoflow Control (see Figure 1-1)
    2. 7.2 Auto-RTS (see Figure 1-1)
    3. 7.3 Auto-CTS (see Figure 1-1)
    4. 7.4 Enabling Autoflow Control and Auto-CTS
    5. 7.5 Auto-CTS and Auto-RTS Functional Timing
    6. 7.6 Functional Block Diagram
    7. 7.7 Principles of Operation
      1. 7.7.1  Accessible Registers
      2. 7.7.2  FIFO Control Register (FCR)
      3. 7.7.3  FIFO Interrupt Mode Operation
      4. 7.7.4  FIFO Polled Mode Operation
      5. 7.7.5  Interrupt Enable Register (IER)
      6. 7.7.6  Interrupt Identification Register (IIR)
      7. 7.7.7  Line Control Register (LCR)
      8. 7.7.8  Line Status Register (LSR)
      9. 7.7.9  Modem Control Register (MCR)
      10. 7.7.10 Modem Status Register (MSR)
      11. 7.7.11 Programming Baud Generator
      12. 7.7.12 Receiver Buffet Register (RBR)
      13. 7.7.13 Scratch Register
      14. 7.7.14 Transmitter Holding Register (THR)
  8. 8 Application Information
  9. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7.3 FIFO Interrupt Mode Operation

When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt occurs as follows:

  1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
  2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the interrupt, it is cleared when the FIFO drops below the trigger level.
  3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04) interrupt.
  4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO. It is cleared when the FIFO is empty.

When the receiver FIFO and receiver interrupts are enabled:

    • At least one character is in the FIFO.
    • The most recent serial character was received more than four continuous character times ago (if two stop bits are programmed, the second one is included in this time delay).
    • The most recent microprocessor read of the FIFO has occurred more than four continuous character times before. This causes a maximum character received command to interrupt an issued delay of 160 ms at a 300 baud rate with a 12-bit character.
  2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional to the baud rate).
  3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads one character from the receiver FIFO.
  4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received or after the microprocessor reads the receiver FIFO.

When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as follows:

  1. The transmitter holding register empty interrupt [IIR (3 −0) = 2] occurs when the transmit FIFO is empty. It is cleared [IIR (3 −0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO while servicing this interrupt) or the IIR is read.
  2. The transmitter holding register empty interrupt is delayed one character time minus the last stop bit time when there have not been at least two bytes in the transmitter FIFO at the same time since the last time that the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.