The system programmer controls the format
of the asynchronous data communication exchange through the LCR. In addition, the
programmer is able to retrieve, inspect, and modify the contents of the LCR; this
eliminates the need for separate storage of the line characteristics in system memory.
The contents of this register are summarized in Table 7-3 and described in the following bulleted list.
- Bits 0 and 1: These two bits specify
the number of bits in each transmitted or received serial character. These bits are
encoded as shown in Table 7-6.
Table 7-6 Serial Character Word
Length
| BIT 1 |
BIT 0 |
WORD LENGTH |
| 0 |
0 |
5 bits |
| 0 |
1 |
6 bits |
| 1 |
0 |
7 bits |
| 1 |
1 |
8 bits |
- Bit 2: This bit specifies either
one, one and one-half, or two stop bits in each transmitted character. When bit
2 is cleared, one stop bit is generated in the data. When bit 2 is set, the
number of stop bits generated is dependent on the word length selected with bits
0 and 1. The receiver clocks only the first stop bit regardless of the number of
stop bits selected. The number of stop bits generated in relation to word length
and bit 2 are shown in Table 7-7.
Table 7-7 Number of Stop Bits
Generated
| BIT 2 |
WORD LENGTH SELECTED BY BITS 1 AND 2 |
NUMBER OF STOP BITS
GENERATED |
| 0 |
Any word length |
1 |
| 1 |
5 bits |
1 1/2 |
| 1 |
6 bits |
2 |
| 1 |
7 bits |
2 |
| 1 |
8 bits |
2 |
- Bit 3: This bit is the parity enable
bit. When bit 3 is set, a parity bit is generated in transmitted data between the
last data word bit and the first stop bit. In received data, if bit 3 is set, parity
is checked. When bit 3 is cleared, no parity is generated or checked.
- Bit 4: This bit is the even parity
select bit. When parity is enabled (bit 3 is set) and bit 4 is set even parity (an
even number of logic 1s in the data and parity bits) is selected. When parity is
enabled and bit 4 is cleared, odd parity (an odd number of logic 1s) is
selected.
- Bit 5: This bit is the stick parity
bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is
transmitted and checked as set. If bit 5 is cleared, stick parity is disabled.
- Bit 6: This bit is the break control
bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT is forced
to the spacing (cleared) state. When bit 6 is cleared, the break condition is
disabled and has no affect on the transmitter logic; it only effects SOUT.
- Bit 7: This bit is the divisor latch
access bit (DLAB). Bit 7 must be set to access the divisor latches of the baud
generator during a read or write. Bit 7 must be cleared during a read or write to
access the receiver buffer, the THR, or the IER.