SLOS154C December   1995  – July 2025 TLC27L1 , TLC27L1A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Dissipation Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Electrical Characteristics, C Suffix
    5. 5.5  Operating Characteristics, VDD = 5V, C Suffix
    6. 5.6  Operating Characteristics, VDD = 10V, C Suffix
    7. 5.7  Electrical Characteristics, I Suffix
    8. 5.8  Operating Characteristics, VDD = 5V, I Suffix
    9. 5.9  Operating Characteristics, VDD = 10V, I Suffix
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Single-Supply Versus Split-Supply Test Circuits
    2. 6.2 Input Bias Current
    3. 6.3 Low-Level Output Voltage
    4. 6.4 Input Offset Voltage Temperature Coefficient
    5. 6.5 Full-Power Response
    6. 6.6 Test Time
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Single-Supply Operation
      2. 7.1.2 Input Characteristics
      3. 7.1.3 Noise Performance
      4. 7.1.4 Feedback
      5. 7.1.5 Electrostatic Discharge Protection
      6. 7.1.6 Latch-Up
      7. 7.1.7 Output Characteristics
      8. 7.1.8 Typical Applications
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TLC27L1 TLC27L1A D Package,8-Pin SOIC, or P Package, 8-Pin PDIP (Top View) Figure 4-1 D Package,8-Pin SOIC, or P Package, 8-Pin PDIP (Top View)
Table 4-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
GND 4 Ground Ground or negative (lowest) power supply
IN+ 3 Input Noninverting input
IN– 2 Input Inverting input
OFFSET N1 1 Input On legacy silicon: IN– offset adjustment pin (bias-select). On new silicon: NC, non internally connected pin
OFFSET N2 5 Input On legacy silicon: IN+ offset adjustment pin (bias-select). On new silicon: NC, non internally connected pin
OUT 6 Output Output
VDD 7, 8 Power Positive (highest) power supply