SLFS043I September 1983 – July 2019 TLC555
The clock input must have VOL and VOH levels that are less than and greater than 1/3 VDD, respectively. Clock input VOL time must be less than minimum output high time, therefore a high (positive) duty cycle clock is recommended. Minimum recommended modulation voltage is 1 V. Lower CONT voltage can greatly increase threshold comparator’s propagation delay and storage time. The application must be tolerant of a nonlinear transfer function; the relationship between modulation input and pulse width is not linear because the capacitor charge is RC based with an negative exponential curve.