Figure 7-1 shows the resistive-load test circuit and voltage waveforms. One can see from Figure 7-1 that with G held low and SRCLR held high, the
status of each drain changes on the rising edge of the register clock, indicating the
transfer of data to the output buffers at that time.
CL includes probe and jig
Figure 7-1 Resistive-Load
Test Circuit and Voltage Waveforms
Figure 7-2 shows the reverse recovery current test circuit and waveforms of source to
Figure 7-2 Reverse Recovery Current Test Circuit
and Waveforms of Source to Drain Diode
Note: A. The VGG amplitude and
RG are adjusted for di/dt = 14 A/μs. A VGG double-pulse train is
used to set IF = 0.35 A, where t1 = 10 μs, t2 = 7 μs, and
t3 = 3 μs.
Note: B. The DRAIN terminal under test is
connected to the TP K test point. All other terminals are connected together and connected
to the TP A test point.
Note: C. IRM = maximum recovery
Figure 7-3 shows the single pulse avalanche energy test circuit and waveforms.
Figure 7-3 Single Pulse Avalanche Energy Test
Circuit and Waveforms
Note: A. The MCU has the following
characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
Note: B. Input pulse duration, tw, is increased
until peak current IAS = 500 mA.
Energy test level is defined as EAS = (IAS × V(BR)DSX ×
tav)/2 = 90 mJ.