SLIS187 June 2021 TLC6A598
Refer to the PDF data sheet for device specific package drawings
Figure 6-1 shows the resistive-load test circuit and voltage waveforms. One can see from the figure that with G held low and SRCLR held high, the status of each drain changes on the rising edge of the register clock, indicating the transfer of data to the output buffers at that time.
Figure 6-2 shows the SER IN to SER OUT waveform. The output signal appears on the falling edge of the shift register clock (SRCK) because there is a phase inverter at SER OUT (see Functional Block Diagram). As a result, it takes seven and a half periods of SRCK for data to transfer from SER IN to SER OUT.
Figure 6-3 shows the test circuit, switching times and voltage waveforms.