SLIS187 June   2021 TLC6A598

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Waveforms
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial-In Interface
      2. 8.3.2 Clear Registers
      3. 8.3.3 Output Channels
      4. 8.3.4 Register Clock
      5. 8.3.5 Cascade Through SER OUT
      6. 8.3.6 Output Control
      7. 8.3.7 Clamping Structure
      8. 8.3.8 Protection Functions
        1. 8.3.8.1 Over Current Protection
        2. 8.3.8.2 Output Detection
        3. 8.3.8.3 Serial Communication Error
        4. 8.3.8.4 Thermal Shutdown
      9. 8.3.9 Interface
        1. 8.3.9.1 Register Write
        2. 8.3.9.2 Register Read
        3. 8.3.9.3 Shift-Register Communication-Fault Detection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VCC < 3 V
      2. 8.4.2 Operation With 5.5 V ≤ VCC ≤ 7 V
    5. 8.5 Register Maps
      1. 8.5.1 Configuration Register(Offset=0h)[reset=0h]
      2. 8.5.2 Fault Readback Register(Offset=1h)[reset=0h]
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application 1
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
    3. 9.3 Typical Application 2
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
    4. 9.4 Typical Application 3
      1. 9.4.1 Design Requirements
      2. 9.4.2 Detailed Design Procedure
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DW|24
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Register Maps

Table 8-1 Register Map
CONFIGURATION REGISTER
Field name DRAIN7 DRAIN6 DRAIN5 DRAIN4 DRAIN3 DRAIN2 DRAIN1 DRAIN0
Default value 0h 0h 0h 0h 0h 0h 0h 0h
Bit 7 6 5 4 3 2 1 0
FAULT READBACK REGISTER
Bit 23 22 21 20 19 18 17 16
Field name DRAIN7_OCP DRAIN6_OCP DRAIN5_OCP DRAIN4_OCP DRAIN3_OCP DRAIN2_OCP DRAIN1_OCP DRAIN0_OCP
Default value 0h 0h 0h 0h 0h 0h 0h 0h
Bit 15 14 13 12 11 10 9 8
Field name DRAIN7_OorS DRAIN6_OorS DRAIN5_OorS DRAIN4_OorS DRAIN3_OorS DRAIN2_OorS DRAIN1_OorS DRAIN0_OorS
Default value 0h 0h 0h 0h 0h 0h 0h 0h
Bit 7 6 5 4 3 2 1 0
Field name TBD TSD CRC
Default value 0h 0h 0h

Table 8-2 lists the memory-mapped registers for the interface.

Table 8-2 Interface Registers
OFFSET ACRONYM REGISTER NAME SECTION
0h Config Configuration Register
1h Fault_Readback Fault Readback Register

Table 8-3 Interface Access Type Codes
CODE DESCRIPTION
Read type R Read-only
Read to clear RC Read to clear the fault
Write W Write-only
Reset or Default Value -n Value after reset or the default value