SLIS187 June 2021 TLC6A598
Refer to the PDF data sheet for device specific package drawings
The TLC6A598 device provides a cyclic redundancy check to verify register values in the shift registers. In read back mode, the TLC6A598 device provides 6 bits of the CRC remainder. The MCU can read back the CRC remainder and check if the remainder is correct. The CRC checksum provides a read back method to verify shift register values without altering them.
The TLC6A598 device also checks the configuration register for faulty commands. The TLC6A598 configuration register consists of 8 bits. To generate the CRC checksum, the device first shifts left 6 bits and appends 0s, then bit-wise exclusive-ORs the 14 data bits with the polynomial to get the checksum.
For example, if the configuration data is 0xFF and the polynomial is 0x43 (7’b1000011), the CRC checksum is 0x0D (6’b00 1101).
The MCU can read back the CRC checksum and append it to the LSB of 8 bits, and then the 14 bits of data becomes 0x3FCD. Performing the bit-wise exclusive-OR operation with the polynomial should lead to a residual of 0.