SLVS561L December   2004  – October 2014 TLV1117

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Handling Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 TLV1117C Electrical Characteristics
    4. 6.4 TLV1117I Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 NPN Output Drive
      2. 7.3.2 Overload Block
      3. 7.3.3 Programmable Feedback
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal operation
      2. 7.4.2 Operation With Low Input Voltage
      3. 7.4.3 Operation at Light Loads
      4. 7.4.4 Operation in Self Protection
  8. Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
      3. 8.1.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • KVU|3
  • DRJ|8
  • DCY|4
  • KCS|3
  • KCT|3
  • KTT|3
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Continuous input voltage 16 V
TJ Operating virtual-junction temperature 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.1 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –65 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 0 2500 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 0 1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 Recommended Operating Conditions

MIN(1) MAX UNIT
VIN Input voltage TLV1117 2.7 15 V
TLV1117-15 2.9 15
TLV1117-18 3.2 15
TLV1117-25 3.9 15
TLV1117-33 4.7 15
TLV1117-50 6.4 15
IO Output current 0.8 A
TJ Operating virtual-junction temperature TLV1117C 0 125 °C
TLV1117I –40 125
(1) The input-to-output differential across the regulator should provide for some margin against regulator operation at the maximum dropout (for a particular current value). This margin is needed to account for tolerances in both the input voltage (lower limit) and the output voltage (upper limit). The absolute minimum VIN for a desired maximum output current can be calculated by the following:
VIN(min) = VOUT(max) + VDO(max at rated current)

Thermal Information

THERMAL METRIC(1)(2)(1) TLV1117 UNITS
PowerFlex DRJ
(8 PINS)
DCY
(4 PINS)
KVU
(3 PINS)
KCS, KCT
(3 PINS)
KTT
(3 PINS)
KTE
(3 PINS)
KTP
(3 PINS)
RθJA Junction-to-ambient thermal resistance 38.6 49.2 38.3 104.3 50.9 30.1 27.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 34.7 60.6 36.5 53.7 57.9 44.6 43.2
RθJB Junction-to-board thermal resistance 3.2 3.1 60.5 5.7 34.8 1.2 17.3
ψJT Junction-to-top characterization parameter 5.9 8.7 0.2 3.1 6 5 2.8
ψJB Junction-to-board characterization parameter 3.1 3 12 5.5 23.7 1.2 9.3
RθJC(bot) Junction-to-case (bottom) thermal resistance 3 3 4.7 n/a 0.4 0.4 0.3
RθJP Thermal resistance between the die junction and the bottom of the exposed pad. 2.7 1.4 1.78 n/a n/a 3 1.94
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(1) Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA) / θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.

6.3 TLV1117C Electrical Characteristics

TJ = 0°C to 125°C, all typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
Reference voltage, VREF VIN – VOUT = 2 V, IOUT = 10 mA, TJ = 25°C TLV1117 1.238 1.25 1.262 V
VIN – VOUT = 1.4 V to 10 V, IOUT = 10 mA to 800 mA 1.225 1.25 1.27
Output voltage, VOUT VIN = 3.5 V, IOUT = 10 mA, TJ = 25°C TLV1117-15 1.485 1.5 1.515
VIN = 2.9 V to 10 V, IOUT = 0 to 800 mA 1.455 1.5 1.545
VIN = 3.8 V, IOUT = 10 mA, TJ = 25°C TLV1117-18 1.782 1.8 1.818
VIN = 3.2 V to 10 V, IOUT = 0 to 800 mA 1.746 1.8 1.854
VIN = 4.5 V, IOUT = 10 mA, TJ = 25°C TLV1117-25 2.475 2.5 2.525
VIN = 3.9 V to 10 V, IOUT = 0 to 800 mA 2.450 2.5 2.550
VIN = 5 V, IOUT = 10 mA, TJ = 25°C TLV1117-33 3.267 3.3 3.333
VIN = 4.75 V to 10 V, IOUT = 0 to 800 mA 3.235 3.3 3.365
VIN = 7 V, IOUT = 10 mA, TJ = 25°C TLV1117-50 4.950 5.0 5.050
VIN = 6.5 V to 12 V, IOUT = 0 to 800 mA 4.900 5.0 5.100
Line regulation IOUT = 10 mA, VIN – VOUT = 1.5 V to 13.75 V TLV1117 0.035% 0.2%
IOUT = 0 mA, VIN = 2.9 V to 10 V TLV1117-15 1 6 mV
IOUT = 0 mA, VIN = 3.2 V to 10 V TLV1117-18 1 6
IOUT = 0 mA, VIN = 3.9 V to 10 V TLV1117-25 1 6
IOUT = 0 mA, VIN = 4.75 V to 15 V TLV1117-33 1 6
IOUT = 0 mA, VIN = 6.5 V to 15 V TLV1117-50 1 10
Load regulation IOUT = 10 mA to 800 mA, VIN – VOUT = 3 V TLV1117 0.2% 0.4%
IOUT = 0 to 800 mA, VIN = 2.9 V TLV1117-15 1 10 mV
IOUT = 0 to 800 mA, VIN = 3.2 V TLV1117-18 1 10
IOUT = 0 to 800 mA, VIN = 3.9 V TLV1117-25 1 10
IOUT = 0 to 800 mA, VIN = 4.75 V TLV1117-33 1 10
IOUT = 0 to 800 mA, VIN = 6.5 V TLV1117-50 1 15
Dropout voltage, VDO(2) IOUT = 100 mA 1.1 1.2 V
IOUT = 500 mA 1.15 1.25
IOUT = 800 mA 1.2 1.3
Current limit VIN – VOUT = 5 V, TJ = 25°C(3) 0.8 1.2 1.6 A
Minimum load current VIN = 15 V TLV1117 1.7 5 mA
Quiescent current VIN ≤ 15 V All fixed-voltage options 5 10 mA
Thermal regulation 30-ms pulse, TA = 25°C 0.01 0.1 %/W
Ripple rejection VIN – VOUT = 3 V, Vripple = 1 Vpp, f = 120 Hz 60 75 dB
ADJ pin current 80 120 μA
Change in ADJ pin current VIN – VOUT = 1.4 V to 10 V, IOUT = 10 mA to 800 mA 0.2 5 μA
Temperature stability TJ = full range 0.5%
Long-term stability 1000 hrs, No load, TA = 125°C 0.3%
Output noise voltage
(% of VOUT)
f = 10 Hz to 100 kHz 0.003%
(1) All characteristics are measured with a 10-μF capacitor across the input and a 10-μF capacitor across the output. Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible.
(2) Dropout is defined as the VIN to VOUT differential at which VOUT drops 100 mV below the value of VOUT,
measured at VIN = VOUT(nom) + 1.5 V.
(3) Current limit test specified under recommended operating conditions.

6.4 TLV1117I Electrical Characteristics

TJ = –40°C to 125°C, all typical values are at TJ = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
Reference voltage, VREF VIN – VOUT = 2 V, IOUT = 10 mA, TJ = 25°C TLV1117 1.238 1.25 1.262 V
VIN – VOUT = 1.4 V to 10 V, IOUT = 10 mA to 800 mA 1.200 1.25 1.29
Output voltage, VOUT VIN = 3.5 V, IOUT = 10 mA, TJ = 25°C TLV1117-15 1.485 1.5 1.515
VIN = 2.9 V to 10 V, IOUT = 0 to 800 mA 1.44 1.5 1.56
VIN = 3.8 V, IOUT = 10 mA, TJ = 25°C TLV1117-18 1.782 1.8 1.818
VIN = 3.2 V to 10 V, IOUT = 0 to 800 mA 1.728 1.8 1.872
VIN = 4.5 V, IOUT = 10 mA, TJ = 25°C TLV1117-25 2.475 2.5 2.525
VIN = 3.9 V to 10 V, IOUT = 0 to 800 mA 2.4 2.5 2.6
VIN = 5 V, IOUT = 10 mA, TJ = 25°C TLV1117-33 3.267 3.3 3.333
VIN = 4.75 V to 10 V, IOUT = 0 to 800 mA 3.168 3.3 3.432
VIN = 7 V, IOUT = 10 mA, TJ = 25°C TLV1117-50 4.95 5.0 5.05
VIN = 6.5 V to 12 V, IOUT = 0 to 800 mA 4.80 5.0 5.20
Line regulation IOUT = 10 mA, VIN – VOUT = 1.5 V to 13.75 V TLV1117 0.035% 0.3%
IOUT = 0 mA, VIN = 2.9 V to 10 V TLV1117-15 1 10 mV
IOUT = 0 mA, VIN = 3.2 V to 10 V TLV1117-18 1 10
IOUT = 0 mA, VIN = 3.9 V to 10 V TLV1117-25 1 10
IOUT = 0 mA, VIN = 4.75 V to 15 V TLV1117-33 1 10
IOUT = 0 mA, VIN = 6.5 V to 15 V TLV1117-50 1 15
Load regulation IOUT = 10 mA to 800 mA, VIN – VOUT = 3 V TLV1117 0.2% 0.5%
IOUT = 0 to 800 mA, VIN = 2.9 V TLV1117-15 1 15 mV
IOUT = 0 to 800 mA, VIN = 3.2 V TLV1117-18 1 15
IOUT = 0 to 800 mA, VIN = 3.9 V TLV1117-25 1 15
IOUT = 0 to 800 mA, VIN = 4.75 V TLV1117-33 1 15
IOUT = 0 to 800 mA, VIN = 6.5 V TLV1117-50 1 20
Dropout voltage, VDO(2) IOUT = 100 mA 1.1 1.3 V
IOUT = 500 mA 1.15 1.35
IOUT = 800 mA 1.2 1.4
Current limit VIN – VOUT = 5 V, TJ = 25°C(3) 0.8 1.2 1.6 A
Minimum load current VIN = 15 V TLV1117 1.7 5 mA
Quiescent current VIN ≤ 15 V All fixed-voltage options 5 15 mA
Thermal regulation 30-ms pulse, TA = 25°C 0.01 0.1 %/W
Ripple rejection VIN – VOUT = 3 V, Vripple = 1 Vpp, f = 120 Hz 60 75 dB
ADJ pin current 80 120 μA
Change in ADJ pin current VIN – VOUT = 1.4 V to 10 V, IOUT = 10 mA to 800 mA 0.2 10 μA
Temperature stability TJ = full range 0.5%
Long-term stability 1000 hrs, No load, TA = 125°C 0.3%
Output noise voltage
(% of VOUT)
f = 10 Hz to 100 kHz 0.003%
(1) All characteristics are measured with a 10-μF capacitor across the input and a 10-μF capacitor across the output. Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible.
(2) Dropout is defined as the VIN to VOUT differential at which VOUT drops 100 mV below the value of VOUT,
measured at VIN = VOUT(nom) + 1.5 V.
(3) Current limit test specified under recommended operating conditions

6.5 Typical Characteristics

g_ssc_vdif_lvs561.gifFigure 1. Short-Circuit Current vs (VIN – VOUT)
g_rr_freq_lvs561.gifFigure 3. Ripple Rejection vs Frequency (ADJ Version)
g_temp_stbl_lvs561.gifFigure 5. Temperature Stability
g_ld_tr_lvs561.gifFigure 7. TLV1117-33 Load Transient Response
g_ldreg_temp_lvs561.gifFigure 2. Load Regulation
g_rr_curr_lvs561.gifFigure 4. Ripple Rejection vs Load Current (ADJ Version)
g_iadj_temp_lvs561.gifFigure 6. ADJ Pin Current vs Temperature
g_ln_tr_lvs561.gifFigure 8. TLV1117-33 Line Transient Response