SBASA91 December   2020 TLV320ADC3120

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: I2C Interface
    7. 7.7  Switching Characteristics: I2C Interface
    8. 7.8  Timing Requirements: TDM, I2S or LJ Interface
    9. 7.9  Switching Characteristics: TDM, I2S or LJ Interface
    10. 7.10 Timing Requirements: PDM Digital Microphone Interface
    11. 7.11 Switching Characteristics: PDM Digial Microphone Interface
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Serial Interfaces
        1. 8.3.1.1 Control Serial Interfaces
        2. 8.3.1.2 Audio Serial Interfaces
          1. 8.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 8.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 8.3.1.2.3 Left-Justified (LJ) Interface
        3. 8.3.1.3 Using Multiple Devices With Shared Buses
      2. 8.3.2 Phase-Locked Loop (PLL) and Clock Generation
      3. 8.3.3 Input Channel Configurations
      4. 8.3.4 Reference Voltage
      5. 8.3.5 Programmable Microphone Bias
      6. 8.3.6 Signal-Chain Processing
        1. 8.3.6.1 Programmable Channel Gain and Digital Volume Control
        2. 8.3.6.2 Programmable Channel Gain Calibration
        3. 8.3.6.3 Programmable Channel Phase Calibration
        4. 8.3.6.4 Programmable Digital High-Pass Filter
        5. 8.3.6.5 Programmable Digital Biquad Filters
        6. 8.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 8.3.6.7 Configurable Digital Decimation Filters
          1. 8.3.6.7.1 Linear Phase Filters
            1. 8.3.6.7.1.1 Sampling Rate: 8 kHz or 7.35 kHz
            2. 8.3.6.7.1.2 Sampling Rate: 16 kHz or 14.7 kHz
            3. 8.3.6.7.1.3 Sampling Rate: 24 kHz or 22.05 kHz
            4. 8.3.6.7.1.4 Sampling Rate: 32 kHz or 29.4 kHz
            5. 8.3.6.7.1.5 Sampling Rate: 48 kHz or 44.1 kHz
            6. 8.3.6.7.1.6 Sampling Rate: 96 kHz or 88.2 kHz
            7. 8.3.6.7.1.7 Sampling Rate: 192 kHz or 176.4 kHz
            8. 8.3.6.7.1.8 Sampling Rate: 384 kHz or 352.8 kHz
            9. 8.3.6.7.1.9 Sampling Rate 768 kHz or 705.6 kHz
          2. 8.3.6.7.2 Low-Latency Filters
            1. 8.3.6.7.2.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.7.2.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.7.2.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.7.2.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.7.2.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.6.7.2.6 Sampling Rate 192 kHz or 176.4 kHz
          3. 8.3.6.7.3 Ultra-Low Latency Filters
            1. 8.3.6.7.3.1 Sampling Rate: 16 kHz or 14.7 kHz
            2. 8.3.6.7.3.2 Sampling Rate: 24 kHz or 22.05 kHz
            3. 8.3.6.7.3.3 Sampling Rate: 32 kHz or 29.4 kHz
            4. 8.3.6.7.3.4 Sampling Rate: 48 kHz or 44.1 kHz
            5. 8.3.6.7.3.5 Sampling Rate: 96 kHz or 88.2 kHz
            6. 8.3.6.7.3.6 Sampling Rate 192 kHz or 176.4 kHz
            7. 8.3.6.7.3.7 Sampling Rate 384 kHz or 352.8 kHz
      7. 8.3.7 Automatic Gain Controller (AGC)
      8. 8.3.8 Digital PDM Microphone Record Channel
      9. 8.3.9 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode or Software Shutdown
      2. 8.4.2 Active Mode
      3. 8.4.3 Software Reset
    5. 8.5 Programming
      1. 8.5.1 Control Serial Interfaces
        1. 8.5.1.1 I2C Control Interface
          1. 8.5.1.1.1 General I2C Operation
          2. 8.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 8.5.1.1.2.1 I2C Single-Byte Write
            2. 8.5.1.1.2.2 I2C Multiple-Byte Write
            3. 8.5.1.1.2.3 I2C Single-Byte Read
            4. 8.5.1.1.2.4 I2C Multiple-Byte Read
    6. 8.6 Register Maps
      1. 8.6.1 Device Configuration Registers
        1. 8.6.1.1 TLV320ADC3120 Access Codes
      2. 8.6.2 Page 0 Registers
      3. 8.6.3 Page 1 Registers
      4. 8.6.4 Programmable Coefficient Registers
        1. 8.6.4.1 Programmable Coefficient Registers: Page 2
        2. 8.6.4.2 Programmable Coefficient Registers: Page 3
        3. 8.6.4.3 Programmable Coefficient Registers: Page 4
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Two-Channel Analog Microphone Recording
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Example Device Register Configuration Script for EVM Setup
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Four-Channel Digital PDM Microphone Recording
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Example Device Register Configuration Script for EVM Setup
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Page 1 Registers

GUID-20201210-SS0T-Z9NR-JK4Q-NHV4TG84GK6Z.html#SBASA91_PAGE_1_TABLE_1 lists the memory-mapped registers for the Page 1 registers. All register offset addresses not listed in GUID-20201210-SS0T-Z9NR-JK4Q-NHV4TG84GK6Z.html#SBASA91_PAGE_1_TABLE_1 should be considered as reserved locations and the register contents should not be modified.

Table 8-107 PAGE 1 Registers
AddressAcronymRegister NameReset ValueSection
0x0PAGE_CFGDevice page register0x00GUID-20201210-SS0T-Z9NR-JK4Q-NHV4TG84GK6Z.html#SBASA91_PAGE_1_PAGE_1_PAGE_CFG
0x1EVAD_CFG1Voice activity detection configuration register 10x20GUID-20201210-SS0T-Z9NR-JK4Q-NHV4TG84GK6Z.html#SBASA91_PAGE_1_PAGE_1_VAD_CFG1
0x1FVAD_CFG2Voice activity detection configuration register 20x08GUID-20201210-SS0T-Z9NR-JK4Q-NHV4TG84GK6Z.html#SBASA91_PAGE_1_PAGE_1_VAD_CFG2

8.6.3.1 PAGE_CFG Register (Address = 0x0) [Reset = 0x0]

PAGE_CFG is shown in GUID-20201210-SS0T-Z9NR-JK4Q-NHV4TG84GK6Z.html#SBASA91_PAGE_1_PAGE_1_PAGE_CFG_FIGURE and described in GUID-20201210-SS0T-Z9NR-JK4Q-NHV4TG84GK6Z.html#SBASA91_PAGE_1_PAGE_1_PAGE_CFG_TABLE.

Return to the Summary Table.

The device memory map is divided into pages. This register sets the page.

Figure 8-127 PAGE_CFG Register
76543210
PAGE[7:0]
R/W-00000000b
Table 8-108 PAGE_CFG Register Field Descriptions
BitFieldTypeResetDescription
7-0PAGE[7:0]R/W00000000bThese bits set the device page.
0d = Page 0
1d = Page 1
2d to 254d = Page 2 to page 254 respectively
255d = Page 255

8.6.3.2 VAD_CFG1 Register (Address = 0x1E) [Reset = 0x20]

VAD_CFG1 is shown in GUID-20201210-SS0T-Z9NR-JK4Q-NHV4TG84GK6Z.html#SBASA91_PAGE_1_PAGE_1_VAD_CFG1_FIGURE and described in GUID-20201210-SS0T-Z9NR-JK4Q-NHV4TG84GK6Z.html#SBASA91_PAGE_1_PAGE_1_VAD_CFG1_TABLE.

Return to the Summary Table.

This register is configuration register 1 for voice activity detection.

Figure 8-128 VAD_CFG1 Register
76543210
VAD_MODE[1:0]VAD_CH_SEL[1:0]VAD_CLK_CFG[1:0]VAD_EXT_CLK_CFG[1:0]
R/W-00bR/W-10bR/W-00bR/W-00b
Table 8-109 VAD_CFG1 Register Field Descriptions
BitFieldTypeResetDescription
7-6VAD_MODE[1:0]R/W00bAuto ADC power up / power down configuration selection.
0d = User initiated ADC power-up and ADC power-down
1d = VAD interrupt based ADC power up and ADC power down
2d = VAD interrupt based ADC power up but user initiated ADC power down
3d = User initiated ADC power-up but VAD interrupt based ADC power down
5-4VAD_CH_SEL[1:0]R/W10bVAD channel select.
0d = Channel 1 is monitored for VAD activity
1d = Channel 2 is monitored for VAD activity
2d = Channel 3 is monitored for VAD activity
3d = Channel 4 is monitored for VAD activity
3-2VAD_CLK_CFG[1:0]R/W00bClock select for VAD
0d = VAD processing using internal oscillator clock
1d = VAD processing using external clock on BCLK input
2d = VAD processing using external clock on MCLK input
3d = Custom clock configuration based on MST_CFG, CLK_SRC and CLKGEN_CFG registers in page 0
1-0VAD_EXT_CLK_CFG[1:0]R/W00bClock configuration using external clock for VAD.
0d = External clock is 3.072 MHz
1d = External clock is 6.144 MHz
2d = External clock is 12.288 MHz
3d = External clock is 18.432 MHz

8.6.3.3 VAD_CFG2 Register (Address = 0x1F) [Reset = 0x8]

VAD_CFG2 is shown in GUID-20201210-SS0T-Z9NR-JK4Q-NHV4TG84GK6Z.html#SBASA91_PAGE_1_PAGE_1_VAD_CFG2_FIGURE and described in GUID-20201210-SS0T-Z9NR-JK4Q-NHV4TG84GK6Z.html#SBASA91_PAGE_1_PAGE_1_VAD_CFG2_TABLE.

Return to the Summary Table.

This register is configuration register 2 for voice activity detection.

Figure 8-129 VAD_CFG2 Register
76543210
RESERVEDSDOUT_INT_CFGRESERVEDRESERVEDVAD_PD_DET_ENRESERVED
R/W-0bR/W-0bR-0bR/W-0bR/W-1bR-000b
Table 8-110 VAD_CFG2 Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDR/W0bReserved bit; Write only reset value
6SDOUT_INT_CFGR/W0bSDOUT interrupt configuration.
0d = SDOUT pin is not enabled for interrupt function
1d = SDOUT pin is enabled to support interrupt output when channel data in not being recorded
5RESERVEDR0bReserved bit; Write only reset value
4RESERVEDR/W0bReserved bit; Write only reset value
3VAD_PD_DET_ENR/W1bEnable ASI output data during VAD activity.
0d = VAD processing is not enabled during ADC recording
1d = VAD processing is enabled during ADC recording and VAD interrupts are generated as configured
2-0RESERVEDR000bReserved bits; Write only reset values