SBASA91A December 2020 – June 2021 TLV320ADC3120
The device has an independent programmable channel gain setting for each input channel that can be set to the appropriate value based on the maximum input signal expected in the system and the ADC VREF setting used (see the Section 8.3.4 section), which determines the ADC full-scale signal level.
Configure the desired channel gain setting before powering up the ADC channel and do not change this setting when the ADC is powered on. The programmable range supported for each channel gain is from 0 dB to 42 dB in steps of 0.5 dB. To achieve low-noise performance, the device internal logic first maximizes the gain for the front-end, low-noise analog PGA, which supports a dynamic range of 120 dB, and then applies any residual programmed channel gain in the digital processing block.
Table 8-13 shows the programmable options available for the channel gain.
|P0_R61_D[7:1] : CH1_GAIN[6:0]||CHANNEL GAIN SETTING FOR INPUT CHANNEL 1|
|000 0000 = 0d (default)||Input channel 1 gain is set to 0 dB|
|000 0001 = 1d||Input channel 1 gain is set to 0.5 dB|
|000 0010 = 2d||Input channel 1 gain is set to 1 dB|
|101 0011 = 83d||Input channel 1 gain is set to 41.5 dB|
|101 0100 = 84d||Input channel 1 gain is set to 42 dB|
|101 0101 to 111 1111 = 85d to 127d||Reserved (do not use these settings)|
Similarly, the channel gain setting for input channel 2 can be configured using the CH2_GAIN (P0_R66_D[7:1]) register bits. The channel gain feature is not available for the digital microphone record path.
The device also supports gain change when the ADC is enabled. The device supports multiple configurations to limit the audible artifacts during dynamic gain change. This feature can be configured by using the OTF_GAIN_CHANGE_CFG (P0_R113_D[7:6]) register bits.
The device also has a programmable digital volume control with a range from –100 dB to +27 dB in steps of 0.5 dB with the option to mute the channel recording. The digital volume control value can be changed dynamically when the ADC channel is powered up and recording. During volume control changes, the soft ramp-up or ramp-down volume feature is used internally to avoid any audible artifacts. Soft-stepping can be entirely disabled using the DISABLE_SOFT_STEP (P0_R108_D4) register bit.
The digital volume control setting is independently available for each output channel, including the digital microphone record channel. However, the device also supports an option to gang-up the volume control setting for all channels together using the channel 1 digital volume control setting, regardless if channel 1 is powered up or powered down. This gang-up can be enabled using the DVOL_GANG (P0_R108_D7) register bit.
Table 8-14 shows the programmable options available for the digital volume control.
|P0_R62_D[7:0] : CH1_DVOL[7:0]||DVC SETTING FOR OUTPUT CHANNEL 1|
|0000 0000 = 0d||Output channel 1 DVC is set to mute|
|0000 0001 = 1d||Output channel 1 DVC is set to –100 dB|
|0000 0010 = 2d||Output channel 1 DVC is set to –99.5 dB|
|0000 0011 = 3d||Output channel 1 DVC is set to –99 dB|
|1100 1000 = 200d||Output channel 1 DVC is set to –0.5 dB|
|1100 1001 = 201d (default)||Output channel 1 DVC is set to 0 dB|
|1100 1010 = 202d||Output channel 1 DVC is set to 0.5 dB|
|1111 1101 = 253d||Output channel 1 DVC is set to 26 dB|
|1111 1110 = 254d||Output channel 1 DVC is set to 26.5 dB|
|1111 1111 = 255d||Output channel 1 DVC is set to 27 dB|
Similarly, the digital volume control setting for output channel 2 to channel 4 can be configured using the CH2_DVOL (P0_R67) to CH4_DVOL (P0_R77) register bits, respectively.
The internal digital processing engine soft ramps up the volume from a muted level to the programmed volume level when the channel is powered up, and the internal digital processing engine soft ramps down the volume from a programmed volume to mute when the channel is powered down. This soft-stepping of volume is done to prevent abruptly powering up and powering down the record channel. This feature can also be entirely disabled using the DISABLE_SOFT_STEP (P0_R108_D4) register bit.