SBASA91A December 2020 – June 2021 TLV320ADC3120
The power-supply sequence between the IOVDD and AVDD rails can be applied in any order. However, after all supplies are stable, then only initiate the I2C transactions to initialize the device.
For the supply power-up requirement, t1 and t2 must be at least 2 ms to allow the device to initialize the internal registers. See the Section 8.4 section for details on how the device operates in various modes after the device power supplies are settled to the recommended operating voltage levels. For the supply power-down requirement, t3 and t4 must be at least 10 ms. This timing (as shown in Figure 10-1) allows the device to ramp down the volume on the record data, power down the analog and digital blocks, and put the device into shutdown mode. The device can also be immediately put into shutdown mode by ramping down power supplies, but doing so causes an abrupt shutdown.
Make sure that the supply ramp rate is slower than 1 V/µs and that the wait time between a power-down and a power-up event is at least 100 ms. For supply ramp rate slower than 0.1 V/ms, host device must apply a software reset as first transaction before doing any device configuration. Make sure all digital input pins are at valid input levels and not toggling during supply sequencing.
The TLV320ADC3120 supports a single AVDD supply operation by integrating an on-chip digital regulator, DREG, and an analog regulator, AREG. However, if the AVDD voltage is less than 1.98 V in the system, then short the AREG and AVDD pins onboard and do not enable the internal AREG by keeping the AREG_SELECT bit to 1b'0 (default value) of P0_R2. If the AVDD supply used in the system is higher than 2.7 V, then the host device can set AREG_SELECT to 1'b1 while exiting sleep mode to allow the device internal regulator to generate the AREG supply.