SLAS510G March   2007  – February 2021 TLV320AIC3104


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Device Comparison Table
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Audio Data Serial Interface Timing Requirements
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagrams
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  Digital Audio Data Serial Interface
        1. Right-Justified Mode
        2. Left-Justified Mode
        3. I2S Mode
        4. DSP Mode
        5. TDM Data Transfer
      3. 10.3.3  Audio Data Converters
        1. Audio Clock Generation
        2. Stereo Audio ADC
          1. Stereo Audio ADC High-Pass Filter
          2. Automatic Gain Control (AGC)
            1. Target Level
            2. Attack Time
            3. Decay Time
            4. Noise Gate Threshold
            5. Maximum PGA Gain Applicable
      4. 10.3.4  Stereo Audio DAC
        1. Digital Audio Processing for Playback
        2. Digital Interpolation Filter
        3. Delta-Sigma Audio DAC
        4. Audio DAC Digital Volume Control
        5. Increasing DAC Dynamic Range
        6. Analog Output Common-Mode Adjustment
        7. Audio DAC Power Control
      5. 10.3.5  Audio Analog Inputs
      6. 10.3.6  Analog Fully Differential Line Output Drivers
      7. 10.3.7  Analog High-Power Output Drivers
      8. 10.3.8  Input Impedance and VCM Control
      9. 10.3.9  MICBIAS Generation
      10. 10.3.10 Short-Circuit Output Protection
      11. 10.3.11 Jack and Headset Detection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Bypass Path Mode
        1. ADC PGA Signal Bypass Path Functionality
        2. Passive Analog Bypass During Power Down
      2. 10.4.2 Digital Audio Processing for Record Path
    5. 10.5 Programming
      1. 10.5.1 I2C Control Interface
        1. I2C Bus Debug in a Glitched System
      2. 10.5.2 Register Map Structure
    6. 10.6 Register Maps
      1. 10.6.1 Output Stage Volume Controls
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Typical Connections With Headphone and External Speaker Driver in Portable Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 11.2.2 Typical Connections for AC-Coupled Headphone Output With Separate Line Outputs and External Speaker Amplifier
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 Support Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Jack and Headset Detection

The TLV320AIC3104 includes extensive capability to monitor a headphone, microphone, or headset jack, determine if a plug has been inserted into the jack, and then determine what type of headset or headphone is wired to the plug. Figure 10-18 illustrates one configuration of the device that enables detection and determination of headset type when a pseudo-differential (capacitor free) stereo headphone output configuration is used. The registers used for this function are page 0, registers 14, 96, 97, and 13. The type of headset detected can be read back from page 0, register 13. Note that for best results, it is recommended to select a MICBIAS value as high as possible, and to program the output driver common-mode level at a 1.35-V or 1.5-V level.

GUID-4F45A5AE-42E9-4EC2-A557-E8D8FFA5D048-low.gifFigure 10-18 Configuration of Device for Jack Detection Using a Pseudo-Differential (Capacitor Free) Headphone Output Connection

A modified output configuration used when the output drivers are ac-coupled is shown in Figure 10-19. In this mode, the device cannot accurately determine if the inserted headphone is a mono or stereo headphone.

GUID-47471640-F0CB-4FF1-AE54-3863B55F7E50-low.gifFigure 10-19 Configuration of Device for Jack Detection Using an AC-Coupled Stereo Headphone Output Connection

An output configuration for the case of the outputs driving fully differential stereo headphones is shown in Figure 10-20. In this mode, there is a requirement on the jack side that either HPLCOM or HPLOUT get shorted to ground if the plug is removed, which can be implemented using a spring terminal in a jack. For this mode to function properly, short-circuit detection should be enabled and configured to power down the drivers if a short-circuit is detected. The registers that control this functionality are in page 0, register 38, bits D2–D1.

GUID-880FD80D-5428-480F-9C0B-3BAD5B657786-low.gifFigure 10-20 Configuration of Device for Jack Detection Using a Fully Differential Stereo Headphone Output Connection