SLAS510G March 2007 – February 2021 TLV320AIC3104
The audio converters in the TLV320AIC3104 need an internal audio master clock at a frequency of 256 fS(ref), which can be obtained in a variety of manners from an external clock signal applied to the device.
A more detailed diagram of the audio clock section of the TLV320AIC3104 is shown in Figure 10-8.
The device can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a programmable divider or a PLL to get the proper internal audio master clock required by the device. The BCLK input can also be used to generate the internal audio master clock.
A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies available in the system. This device includes a highly programmable PLL to accommodate such situations easily. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus paid to the standard MCLK rates already widely used.
When the PLL is disabled,
CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits D7–D6.
In the absence of an MCLK, CLKDIV_IN must receive an active clock for proper functionality. For three-wire I2S, when BCLK is selected for PLL_IN (page 0, register 102), BCLK must also be selected for CLKDIV_IN.
NOTE – when NCODEC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK can be as high as 50 MHz, and fS(ref) should fall within 39 kHz to 53 kHz, inclusive.
When the PLL is enabled,
P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision). P can be set in page 0, register 3, bits D2–D0. R can be set in page 0, register 11, bits D3–D0. J can be set in page 0, register 4, bits D7–D2. The most-significant bits of D can be set in page 0, register 5, bits D7–D0, and the least-significant bits of D can be set in page 0, register 6, bits D7–D2.
If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004
When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified performance:
512 kHz ≤ (PLLCLK_IN/P) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R/P) ≤ 110 MHz
4 ≤ J ≤ 55
When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified performance:
10 MHz ≤ PLLCLK _IN/P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R/P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1
MCLK = 12 MHz and fS(ref) = 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264
MCLK = 12 MHz and fS(ref) = 48 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920
Table 10-1 lists several example cases of typical MCLK rates and how to program the PLL to achieve fS(ref) = 44.1 kHz or 48 kHz.
|MCLK (MHz)||P||R||J||D||ACHIEVED fS(ref)||% ERROR|
|fS(ref) = 44.1 kHz|
|fS(ref) = 48 kHz|