SLVS568E January   2005  – July 2025 TLV341 , TLV341A , TLV342 , TLV342S

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information: TLV341
    5. 5.5  Thermal Information: TLV342
    6. 5.6  Thermal Information: TLV342S
    7. 5.7  Electrical Characteristics: V+ = 1.8V
    8. 5.8  Electrical Characteristics: V+ = 5V
    9. 5.9  Shutdown Characteristics: V+ = 1.8V
    10. 5.10 Shutdown Characteristics: V+ = 5V
    11. 5.11 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 PMOS Input Stage
      2. 6.3.2 CMOS Output Stage
      3. 6.3.3 Shutdown
    4. 6.4 Device Functional Modes
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics: V+ = 5V

V+ = 5V, GND = 0V, VIC = VO = V+/2, RL > 1MΩ (unless otherwise noted). See Section 5.10.
PARAMETERTEST CONDITIONSTAMINTYP(1)MAXUNIT
VIOInput offset voltageStandard grade25°C0.34mV
Full range4.5
A grade25°C0.31.25
0°C to 125°C0.31.5
–40°C to 125°C0.31.7
αVIOAverage temperature coefficient of input offset voltageFull range1.9μV/°C
IIBInput bias current25°C1200pA
–40°C to 85°C375
–40°C to 125°C3000
IIOInput offset current25°C6.6fA
CMRRCommon-mode rejection ratio0 ≤ VICR ≤ 4.4V25°C7590dB
Full range70
kSVRSupply-voltage rejection ratio1.8V ≤ V+ ≤ 5V25°C7595dB
Full range65
VICRCommon-mode input voltage rangeCMRR ≥ 70dB25°C04.4V
AVLarge-signal voltage gain(1)RL = 10kΩ to 2.5V25°C80110dB
Full range70
RL = 2kΩ to 2.5V25°C75105
Full range60
VOOutput swing
(delta from supply rails)
RL = 2kΩ to 2.5VLow level25°C4060mV
Full range85
High level25°C2560
Full range85
RL = 10kΩ to 2.5VLow level25°C1830
Full range40
High level25°C715
Full range20
ICCSupply current (per channel)25°C150200μA
Full range215
IOSOutput short-circuit currentSourcing25°C60113mA
Sinking80115
SRSlew rateRL = 10kΩ(1)25°C1V/μs
GBWUnity-gain bandwidthRL = 10kΩ, CL = 200pF25°C2.3MHz
φmPhase marginRL = 100kΩ, CL = 200pF25°C55°
GmGain marginRL = 100kΩ, CL = 200pF25°C15dB
VnEquivalent input noise voltagef = 1kHz25°C33nV/√ Hz
InEquivalent input noise currentf = 1kHz25°C0.001pA/√ Hz
THDTotal harmonic distortionf = 1kHz, AV = 1, RL = 600Ω,
VI = 1VPP
25°C0.012%