SNVSB04B March   2019  – June 2020 TLV4021 , TLV4031 , TLV4041 , TLV4051

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      TLV40x1 Configurations
  4. Revision History
  5. Pin Configuration and Functions
    1.     DSBGA Package Pin Functions
    2.     SOT-23 Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power ON Reset (POR)
      2. 7.4.2 Input (IN)
      3. 7.4.3 Switching Thresholds and Hysteresis (VHYS)
      4. 7.4.4 Output (OUT)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Monitoring (V+)
      2. 8.1.2 Monitoring a Voltage Other than (V+)
      3. 8.1.3 VPULLUP to a Voltage Other than (V+)
    2. 8.2 Typical Application
      1. 8.2.1 Under-Voltage Detection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Additional Application Information
        1. 8.2.2.1 Pull-up Resistor Selection
        2. 8.2.2.2 Input Supply Capacitor
        3. 8.2.2.3 Sense Capacitor
    3. 8.3 What to Do and What Not to Do
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pull-up Resistor Selection

For the TLV4021 (open-drain output versions of the TLV40x1 family), care should be taken in selecting the pull-up resistor (RPU) value to ensure proper output voltage levels. First, consider the required output high logic level requirement of the logic device that is being driven by the comparator when calculating the maximum RPU value. When in a logic high output state, the output impedance of the comparator is very high but there is a finite amount of leakage current that needs to be accounted for. Use IO-LKG from the EC Table and the VIH minimum from the logic device being driven to determine RPU maximum using Equation 4.

Equation 4. TLV4021 TLV4031 TLV4041 TLV4051 RPU_max.gif

Next, determine the minimum value for RPU by using the VIL maximum from the logic device being driven. In order for the comparator output to be recognized as a logic low, VIL maximum is used to determine the upper boundary of the comparator's VOL. VOL maximum for the comparator is available in the EC Table for specific sink current levels and can also be found from the VOUT versus ISINK curve in the Typical Application curves. A good design practice is to choose a value for VOL maximum that is 1/2 the value of VIL maximum for the input logic device. The corresponding sink current and VOL maximum value will be needed to calculate the minimum RPU. This method will ensure enough noise margin for the logic low level. With VOL maximum determined and the corresponding ISINK obtained, the minimum RPU value is calculated with Equation 5.

Equation 5. TLV4021 TLV4031 TLV4041 TLV4051 RPU_min.gif

Since the range of possible RPU values is large, a value between 5 kΩ and 100 kΩ is generally recommended. A smaller RPU value provides faster output transition time and better noise immunity, while a larger RPU value consumes less power when in a logic low output state.