SNVSB04B March   2019  – June 2020 TLV4021 , TLV4031 , TLV4041 , TLV4051

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      TLV40x1 Configurations
  4. Revision History
  5. Pin Configuration and Functions
    1.     DSBGA Package Pin Functions
    2.     SOT-23 Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power ON Reset (POR)
      2. 7.4.2 Input (IN)
      3. 7.4.3 Switching Thresholds and Hysteresis (VHYS)
      4. 7.4.4 Output (OUT)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Monitoring (V+)
      2. 8.1.2 Monitoring a Voltage Other than (V+)
      3. 8.1.3 VPULLUP to a Voltage Other than (V+)
    2. 8.2 Typical Application
      1. 8.2.1 Under-Voltage Detection
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Additional Application Information
        1. 8.2.2.1 Pull-up Resistor Selection
        2. 8.2.2.2 Input Supply Capacitor
        3. 8.2.2.3 Sense Capacitor
    3. 8.3 What to Do and What Not to Do
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Switching Thresholds and Hysteresis (VHYS)

The TLV40x1 transfer curve is shown in Figure 37.

  • VIT+ represents the positive-going input threshold that causes the comparator output to change from a logic low state to a logic high state.
  • VIT- represents the negative-going input threshold that causes the comparator output to change from a logic high state to a logic low state.
  • VHYS represents the difference between VIT+ and VIT- and is 20 mV for TLV40x1Ry and 54 mV for TLV4021S5.
TLV4021 TLV4031 TLV4041 TLV4051 NonInvHyst.gifFigure 37. Transfer Curve

VIT+ and VIT- have mV's of variation over temperature. The significant portion of the variation of these parameters is a result of the internal bandgap voltage from which VIT+ and VIT- are derived. The following hysteresis histograms demonstrate the performance of the TLV40x1 hysteresis circuitry. Since the bandgap reference is used to set VIT+ and VIT-, each of these parameters have a tendency to error (track) in the same direction. For example, if VIT+ has a positive 0.5% error, VIT- would have a tendency to have a similar positive percentage error. As a result, the variation of hysteresis will never be equal to the difference of the highest VIT+ value of its range and the lowest VIT- value of its range.

TLV4021 TLV4031 TLV4041 TLV4051 Hysteresis_R2_Histogram.gifFigure 38. VHYST Histogram (TLV40x1R2, VS=5V)
TLV4021 TLV4031 TLV4041 TLV4051 Hysteresis_S5_Histogram.gifFigure 40. VHYST Histogram (TLV40x1S5, VS=5V)
TLV4021 TLV4031 TLV4041 TLV4051 Hysteresis_R1_Histogram.gifFigure 39. VHYST Histogram (TLV40x1R1, VS=5V)