RESET remains high (deasserted) as long as VDD is above the negative threshold (VIT–). If VDD falls below the negative threshold (VIT–), then reset is asserted and RESET transistions to logic low (VOL).
When VDD rises above VIT+, the delay circuit holds RESET active and logic low for the specified reset delay period (tD). When the reset delay has elapsed, the RESET pin transistions to high voltage (VOH).
The open-drain version requires an external pull-up resistor to hold the RESET pin high because the internal MOSFET turns off causing RESET output to pull-up to the pull-up voltage. Connect the pull-up resistor to the desired interface voltage logic. RESET can be pulled up to any voltage up to maximum voltage independent of the VDD voltage. To ensure proper voltage levels, take care when choosing the pull-up resistor values. The pull-up resistor value is determined by VOL, the output capacitive loading, and the output leakage current (Ilkg(OD)).
The push-pull variant does not require an external pull-up resistor.