SNVSBY3A November   2020  – April 2021 TLV840-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 User-Programmable Reset Time Delay
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Output Logic
        1. 8.3.4.1 RESET Output, Active-Low
        2. 8.3.4.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: Dual Rail Monitoring with Power-up Sequencing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application Curve: Adjusting Output Reset Delay on TLV840EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.4.2 RESET Output, Active-High

RESET (Active-High), denoted with no bar above the pin label, applies to TLV840DH-Q1 (Open-Drain) and TLV840PH-Q1 push-pull active-high version, hence the "H" in the device name. RESET remains low (deasserted) as long as VDD is above the negative threshold (VIT-) and the MR pin is floating or above VMR_H. If VDD falls below the negative threshold (VIT-) or if MR is driven low, then RESET is asserted driving the RESET pin to high voltage (VOH).

When MR is again logic high or floating and VDD rise above VIT+ the delay circuit will hold RESET high for the specified reset time delay (tD). When the reset time delay has elapsed, the RESET pin goes back to logic low voltage (VOL).

The TLV840DH-Q1 (Open-Drain) version, denoted with "D" in the device name, requires an external pull-up resistor to hold RESET pin high. Connect the external pull-up resistor to the desired pull-up voltage source and RESET can be pulled up to any voltage up to 6.5 V independent of the VDD voltage. To ensure proper voltage levels, give some consideration when choosing the pull-up resistor values. The external pull-up resistor value determines the actual VOL, the output capacitive loading, and the output leakage current (Ilkg(OD)).

The Push-Pull variants (TLV840PL-Q1 and TLV840PH-Q1), denoted with "P" in the device name, does not require an external pull-up resistor.