SLVSFO5D April   2020  – January 2023 TLV841

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 SENSE Input (TLV841S)
        1. 8.3.2.1 SENSE Hysteresis
        2. 8.3.2.2 Immunity to SENSE Pin Voltage Transients
      3. 8.3.3 User-Programmable Reset Time Delay for TLV841C only
      4. 8.3.4 Manual Reset (MR) Input for TLV841M only
      5. 8.3.5 Output Logic
        1. 8.3.5.1 RESET Output, Active-Low
        2. 8.3.5.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves: TLV841EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.5 Electrical Characteristics

At VDDMIN ≤ VDD ≤ 5.5 V, CT = MR = Open, RESET/RESET pull-up resistor Rpull-up (3) = 100 kΩ to VDD, output reset load CLOAD = 10 pF and over the operating free-air temperature range –40℃ to 125℃, unless otherwise noted. Typical values are at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
COMMON PARAMETERS
VADJ-VIT– Negative-going input threshold for TLV841Sxxx01 ADJ version 0.505 V
VIT– Negative-going input threshold range
Fixed threshold version (1) 		0.8 4.9 V
VIT–_ACC Negative-going input threshold accuracy VIT– = 0.505 V (TLV841Sxx01) or 0.8 V to 1.7 V (Fixed threshold) -2.5 ±0.5 2.5 %
VIT– = 1.8 V to 4.9 V (Fixed threshold) -2 ±0.5 2
VHYS Hysteresis on VIT– pin VIT– = 0.505 V and 0.8 V 3 5 8 %
VIT– = 0.9 V to 4.9 V 3 5 7
VPOR Power on reset voltage (2) TLV841xxxLxx VOL(MAX) = 300 mV
I RESET(Sink) = 15 µA		 700 mV
TLV841xxxHxx VOH(MIN) = 0.8VDD
IRESET(Source) = 15 µA		 900
VOL Low level output voltage VDD = 0.85 V
I RESET(Sink) = 15 µA
IRESET(Sink) = 15 µA		 300 mV
VDD = 3.3 V
I RESET(Sink) = 2 mA
IRESET(Sink) = 2 mA		 300 mV
VDD = 5.5 V
I RESET(Sink) = 2 mA
IRESET(Sink) = 2 mA		 300 mV
VOH High level output voltage VDD = 1 V
I RESET(Source) = 15 µA
IRESET(Source) = 15 µA		 0.8VDD V
VDD = 1.8 V
I RESET(Source) = 500 µA
IRESET(Source) = 500 µA		 0.8VDD V
VDD ≥ 3.3 V
I RESET(Source) = 2 mA
IRESET(Source) = 2 mA		 0.8VDD V
Ilkg(OD) Open-Drain output leakage current VDD = VPULLUP = 5.5 V TA = –40℃ to 85℃ 10 100 nA
10 350
IDD Supply current into VDD pin Supply current into VDD pin VDD = 5.5 V
VIT– = 1.9 V to 4.9 V		 0.125 1 µA
TLV841S
ISENSE Current into SENSE pin, fixed threshold variant VDD = VSENSE = 5.5 V
VIT– = 0.8 V to 4.9 V		 0.025 0.1 µA
Current into SENSE pin, ADJ variant VDD = VSENSE = 5.5 V
VIT– = 0.505 V		 0.025 0.05
TLV841M
V MR_L Manual reset logic low input 0.3VDD V
V MR_H Manual reset logic high input 0.7VDD V
R MR Manual reset internal pull-up resistance 100 kΩ
TLV841C
RCT CT pin internal resistance 410 500 590 kΩ
(1) VIT- threshold voltage range from 0.8 V to 4.9 V (for DL, PL, DH) and 1 V to 4.9 V (for PH) in 100 mV steps, for released versions see Device Voltage Thresholds table.
(2) VPOR is the minimum VDD voltage level for a controlled output state. 
(3) Pull up resistance applicable for open drain variants