SLVSFO5D April   2020  – January 2023 TLV841

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 SENSE Input (TLV841S)
        1. 8.3.2.1 SENSE Hysteresis
        2. 8.3.2.2 Immunity to SENSE Pin Voltage Transients
      3. 8.3.3 User-Programmable Reset Time Delay for TLV841C only
      4. 8.3.4 Manual Reset (MR) Input for TLV841M only
      5. 8.3.5 Output Logic
        1. 8.3.5.1 RESET Output, Active-Low
        2. 8.3.5.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves: TLV841EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Timing Requirements

At VDDMIN ≤ VDD ≤ 5.5 V, CT = MR = Open, RESET pull-up resistor Rpull-up = 100 kΩ to VDD, output load is CLOAD = 10 pF and over the operating free-air temperature range –40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tP_HL Propagation detect delay for VDD falling below VIT– VDD = (VIT+ + 10%) to (VIT– – 10%) (2) 30 50 µs
tD Reset time delay (TLV841C variant) CT pin = Open or NC 40 80 µs
CT pin = 10 nF 6.2 ms
CT pin = 1 µF 619 ms
tD Reset time delay (TLV841S and TLV841M variant) (5) Variant A (3) 40 80 µs
Variant B (3) 2 ms
Variant C (3) 10 ms
Variant D (3) 30 ms
Variant E (3) 50 ms
Variant F (3) 80 ms
Variant G (3) 100 ms
Variant H (3) 150 ms
Variant I (3) 200 ms
tGI_VIT– Glitch immunity VIT–
5% VIT– overdrive (4) 		10 µs
tSTRT Startup Delay (1) 300 µs
t MR_RES Propagation delay from MR low to reset VDD = 3.3 V, MR < V MR_L tP_HL µs
t MR_tD Delay from release MR to deassert reset VDD = 3.3 V,
MR = V MR_L to V MR_H   		tD ms
t MR_PW Glitch immunity MR pin 10 µs
(1) When VDD starts from less than the specified minimum VDD and then exceeds VPOR, reset is release after the startup delay (tSTRT). For TLV841C variants a capacitor at CT pin will add tD delay to tSTRT time
(2) tP_HL measured from threhold trip point (VIT–) to VOL for active low variants and VOH for active high variants. 
(3) Refer device nomenclature table for variant description. VDD transition from VIT– – 10% to VIT+ + 10% for TLV841M and TLV841C; VSENSE transition from VIT– – 10% to VIT+ + 10% for TLV841S
(4) Overdrive % = [(VDD/ VIT–) – 1] × 100% for TLV841M and TLV841C; Overdrive % = [(VSENSE/ VIT–) – 1] × 100% for TLV841S
(5) Specified by design and characterization