SBOS836C March   2020  – March 2021 TLV9041 , TLV9042 , TLV9044

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information for Single Channel
    5. 7.5 Thermal Information for Dual Channel
    6. 7.6 Thermal Information for Quad Channel
    7. 7.7 Electrical Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Operating Voltage
      2. 8.3.2  Rail-to-Rail Input
      3. 8.3.3  Rail-to-Rail Output
      4. 8.3.4  Common-Mode Rejection Ratio (CMRR)
      5. 8.3.5  Capacitive Load and Stability
      6. 8.3.6  Overload Recovery
      7. 8.3.7  EMI Rejection
      8. 8.3.8  Electrical Overstress
      9. 8.3.9  Input and ESD Protection
      10. 8.3.10 Shutdown Function
      11. 8.3.11 Packages With an Exposed Thermal Pad
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 TLV904x Low-Side, Current Sensing Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4.     Trademarks
    5. 12.4 Electrostatic Discharge Caution
    6. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

GUID-58A2EDD2-DB57-472A-A3B5-84AE7B42315A-low.svgFigure 6-1 TLV9041 DBV Package
5-Pin SOT-23
Top View
GUID-06B4E520-FF08-4AC2-8455-4DD8B1BE3851-low.svgFigure 6-3 TLV9041 DQN Package
5-Pin X2SON
Top View
GUID-C1B96E2B-930C-41B9-9086-3EA7BD6951F2-low.svgFigure 6-2 TLV9041 DCK Package
5-Pin SC70
Top View
Table 6-1 Pin Functions: TLV9041
PIN I/O DESCRIPTION
NAME NO.
SOT-23 SC70 X2SON
IN– 4 3 2 I Inverting input
IN+ 3 1 4 I Noninverting input
OUT 1 4 1 O Output
V– 2 2 3 I or — Negative (low) supply or ground (for single-supply operation)
V+ 5 5 5 I Positive (high) supply
GUID-9942BCCE-3DE9-4210-9C7E-097D737EA214-low.svg Figure 6-4 TLV9041S DBV Package
6-Pin SOT-23
Top View
Table 6-2 Pin Functions: TLV9041S
PIN I/O DESCRIPTION
NAME NO.
IN– 4 I Inverting input
IN+ 3 I Noninverting input
OUT 1 O Output
SHDN 5 I Shutdown (low), enabled (high)
V– 2 I or — Negative (low) supply or ground (for single-supply operation)
V+ 6 I Positive (high) supply
GUID-8E9A7C42-C6DA-4C20-BA20-2C6217D23BF8-low.svgFigure 6-5 TLV9042 D, DDF, DGK, PW Packages
8-Pin SOIC, SOT-23 8, VSSOP, TSSOP
Top View
GUID-F6592023-B378-49A0-B2D0-5B8B0CEA2F49-low.svg
Connect exposed thermal pad to V–. See Section 8.3.11 for more information.
Figure 6-6 TLV9042 DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
Table 6-3 Pin Functions: TLV9042
PIN I/O DESCRIPTION
NAME NO.
IN1– 2 I Inverting input, channel 1
IN1+ 3 I Noninverting input, channel 1
IN2– 6 I Inverting input, channel 2
IN2+ 5 I Noninverting input, channel 2
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
V– 4 I Negative (low) supply or ground (for single-supply operation)
V+ 8 I Positive (high) supply
GUID-2C1E1E20-92E3-4C62-BC61-BFC1BAD4BC9E-low.svg Figure 6-7 TLV9042S RUG Package
10-Pin X2QFN
Top View
Table 6-4 Pin Functions: TLV9042S
PIN I/O DESCRIPTION
NAME NO.
IN1– 9 I Inverting input, channel 1
IN1+ 10 I Noninverting input, channel 1
IN2– 5 I Inverting input, channel 2
IN2+ 4 I Noninverting input, channel 2
OUT1 8 O Output, channel 1
OUT2 6 O Output, channel 2
SHDN1 2 I Shutdown – low = disabled, high = enabled, channel 1
SHDN2 3 I Shutdown – low = disabled, high = enabled, channel 2
V– 1 I Negative (low) supply or ground (for single-supply operation)
V+ 7 I Positive (high) supply
GUID-D093D7D3-F7EA-4AE5-B57C-205EFD8C8407-low.svg Figure 6-8 TLV9044 D, PW Packages
14-Pin SOIC, TSSOP
Top View
Table 6-5 Pin Functions: TLV9044
PIN I/O DESCRIPTION
NAME NO.
IN1– 2 I Inverting input, channel 1
IN1+ 3 I Noninverting input, channel 1
IN2– 6 I Inverting input, channel 2
IN2+ 5 I Noninverting input, channel 2
IN3– 9 I Inverting input, channel 3
IN3+ 10 I Noninverting input, channel 3
IN4– 13 I Inverting input, channel 4
IN4+ 12 I Noninverting input, channel 4
NC No internal connection
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
V– 11 I or — Negative (low) supply or ground (for single-supply operation)
V+ 4 I Positive (high) supply