SBOS942J August   2018  – February 2024 TLV9051 , TLV9052 , TLV9054

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Rail-to-Rail Input
      3. 7.3.3 Rail-to-Rail Output
      4. 7.3.4 EMI Rejection
      5. 7.3.5 Overload Recovery
      6. 7.3.6 Packages With an Exposed Thermal Pad
      7. 7.3.7 Electrical Overstress
      8. 7.3.8 Input Protection
      9. 7.3.9 Shutdown Function
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Low-Side Current Sense Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8 V to 5.5 V

at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted);
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = 5 V ±0.33 ±1.6 mV
VS = 5 V, TA = –40°C to +125°C ±2
dVOS/dT Drift VS = 5 V, TA = –40°C to +125°C ±0.5 µV/°C
PSRR Power-supply rejection ratio VS = 1.8 V – 5.5 V, VCM = (V–) ±13 ±80 µV/V
Channel separation, dc At dc 115 dB
INPUT VOLTAGE RANGE
VCM Common-mode voltage VS = 1.8 V to 5.5 V (V–) – 0.1 (V+) + 0.1 V
CMRR Common-mode rejection ratio VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to +125°C		 80 96 dB
VS = 5.5 V, VCM = –0.1 V to 5.6 V,
TA = –40°C to +125°C		 62 79
VS = 1.8 V, (V–) – 0.1 V < VCM < (V+) – 1.4 V,
TA = –40°C to +125°C		 88
VS = 1.8 V, VCM = –0.1 V to 1.9 V,
TA = –40°C to +125°C		 72
INPUT BIAS CURRENT
IB Input bias current ±2 ±18(2) pA
TA = –40°C to +125°C ±525(2) pA
IOS Input offset current ±1 ±15(2) pA
TA = –40°C to +125°C ±440(2) pA
NOISE
En Input voltage noise (peak-to-peak) VS = 5 V, f = 0.1 Hz to 10 Hz 6 µVPP
en Input voltage noise density VS = 5 V, f = 10 kHz 15 nV/√Hz
VS = 5 V, f = 1 kHz 20 nV/√Hz
in Input current noise density f = 1 kHz 18 fA/√Hz
INPUT CAPACITANCE
CID Differential 2 pF
CIC Common-mode 4 pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 1.8 V, (V–) + 0.04 V < VO < (V+) – 0.04 V,
RL = 10 kΩ		 106 dB
VS = 5.5 V, (V–) + 0.05 V < VO < (V+) – 0.05 V,
RL = 10 kΩ		 104 128
VS = 1.8 V, (V–) + 0.06 V < VO < (V+) – 0.06 V,
RL = 2 kΩ		 108
VS = 5.5 V, (V–) + 0.15 V < VO < (V+) – 0.15 V,
RL = 2 kΩ		 130
FREQUENCY RESPONSE
GBP Gain bandwidth product VS = 5.5 V, G = +1 5 MHz
φm Phase margin VS = 5.5 V, G = +1 60 Degrees
SR Slew rate VS = 5.5 V, G = +1, CL = 130pF 15 V/µs
tS Settling time To 0.1%, VS = 5.5 V, 2-V step , G = +1, CL = 100 pF 0.75 µs
To 0.01%, VS = 5.5 V, 2-V step , G = +1, CL = 100 pF 1
tOR Overload recovery time VS = 5.5 V, VIN  × gain > VS 0.3 µs
THD + N Total harmonic distortion + noise(1) VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1, f = 1 kHz 0.0006%
OUTPUT
VO Voltage output swing from supply rails VS = 5.5 V, RL = 10 kΩ, 16 mV
VS = 5.5 V, RL = 2 kΩ, 40
ISC Short-circuit current VS = 5 V ±50 mA
ZO Open-loop output impedance VS = 5 V, f = 5 MHz 250 Ω
POWER SUPPLY
IQ Quiescent current per amplifier VS = 5.5 V, IO = 0 mA, 330 450 µA
VS = 5.5 V, IO = 0 mA, TA = –40°C to +125°C 475
SHUTDOWN
IQSD Quiescent current per amplifier VS = 1.8 to 5.5 V, all amplifiers disabled, SHDN = V- 0.35 1 µA
ZSHDN Output impedance VS = 1.8 to 5.5 V, amplifier disabled 10 || 2 GΩ || pF
High-level voltage shutdown threshold (amplifier enabled) VS = 1.8 to 5.5 V (V-) + 0.9 (V-) + 1.1 V
Low-loevel voltage shutdown threshold (amplifeir disabled) VS = 1.8 to 5.5 V (V-) + 0.2 (V-) + 0.7 V
tON Amplifier enabled time (full shutdown (3) (4) 35 µS
tON Amplifier enabled time (partial shutdown ) (3) (4) 10 µS
tOFF Amplifier diabled time (3) 6 µS
SHDN pin input bias current (per pin) VS = 1.8 V to 5.5 V, V+ ≥ (V+) - 0.8 V 6.5 nA
SHDN pin input bias current (per pin) VS = 1.8 V to 5.5 V, V+ ≤ (V-) + 0.8 V 155 nA
(1) Third-order filter; bandwidth = 80 kHz at –3 dB.
(2) Specified by design and characterization; not production tested.
(3) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(4) Full shutdown refers to the dual TLV9052S having both channels 1 and 2 disabled (SHDN1 = SHDN2 = V–) and the quad TLV9054S having all channels 1 to 4 disabled (SHDN12 = SHDN34 = V–). For partial shutdown, only one SHDN pin is exercised; in this mode, the internal biasing circuitry remains operational and the enable time is shorter.